Jorge E Lach

6363452, Mar 26, 2002

Mar 29, 1999

09/280784

Jorge E. Lach - Lexington MA

Sun Microsystems, Inc. - Palo Alto CA

G06F 1300

710316, 710313, 710302

A hot plugging system has a first mechanism for selectively connecting, responsive to a first control signal, each of a plurality of slots with a primary bus, e. g. ,a PCI bus connected to a system bus of a computer system; and a second mechanism for connecting, responsive to a second control signal, at least one of the slots with a secondary bus, e. g. , a dedicated PCI bus, or other connection interface, used for testing purposes during hot-plug insertion of an adapter card. In another aspect, a hot plug controller makes the connection of the at least one slot to the primary bus in response to a BUS_IDLE signal from the host bridge that indicates when the PCI bus is idle. The BUS_IDLE signal can be generated from the FRAME and IRDY signals for the primary bus by combinational logic in the host bridge. In this way, the hot plug controller need not be connected to and load the shared lines, e. g. , the FRAME and IRDY lines, of that bus.

6591322, Jul 8, 2003

Aug 1, 2000

09/630099

Joseph J. Ervin - Stow MA
Jorge E. Lach - Lexington MA

Sun Microsystems, Inc. - Santa Clara CA

G06F 1300

710110, 710314, 711201

A âfirewallâ apparatus is placed between a single bus master device and a multimaster I C bus system. The firewall apparatus transforms all multimaster bus errors into simple NAK errors and isolates the single bus master from the multimaster bus. Therefore the single bus master needs only to retry transactions that receive unexpected NAKs and all complex multimaster issues, such as bus collisions, transaction termination and bus recovery, associated with the actual error that occurred on the multimaster bus are handled by the firewall apparatus. In accordance with one embodiment, when the single bus master attempts to launch a transaction at a time when the multimaster I C bus is busy, the firewall apparatus absorbs the address driven by the single bus master and then stalls the transaction until the firewall apparatus is able to successfully acquire and drive the address on the multimaster bus. The firewall apparatus is implemented in a preferred embodiment by a programmed microcontroller.

20080259555, Oct 23, 2008

Apr 11, 2008

12/101727

Andreas V. Bechtolsheim - Palo Alto CA, US
Jorge E. Lach - Lexington MA, US
Paul G. Phillips - Westborough MA, US

SUN MICROSYSTEMS, INC. - Santa Clara CA

H05K 7/10

361686

A blade server includes a chassis; a first plurality of bays in the chassis, wherein the first plurality of bays is adapted to receive and at least partially house a plurality of CPU modules, and wherein the first plurality of bays is accessible through a first side of the chassis; a second plurality of bays in the chassis, wherein the second plurality of bays is adapted to receive and at least partially house a plurality of PCI-Express modules, and wherein the second plurality of bays is accessible through a second side of the chassis; and a midplane board arranged to pass a PCI-Express signal between at least one of the plurality of CPU modules and at least one of the plurality of PCI-Express modules.

20090089464, Apr 2, 2009

Sep 27, 2007

11/862973

Jorge E. Lach - Lexington MA, US
Paul G. Phillips - Westborough MA, US

Sun Microsystems, Inc. - Santa Clara CA

G06F 13/14

710 62

An apparatus includes a server comprising n operating system images and an IOV aware root complex; a plurality of physical I/O devices comprising n virtual I/O functions; and a PCI Express bus operatively connected to the server and the plurality physical I/O devices via the root complex, wherein the root complex is operable to provide communication between the n operating system images and the n virtual I/O function, and wherein the server and the plurality of physical I/O devices are modules in a chassis.

59094516, Jun 1, 1999

Nov 21, 1996

8/806702

Jorge E. Lach - Lexington MA
Bennet H. Ih - Cambridge MA

Sun Microsystems, Inc. - Palo Alto CA

H04B 1700

371 2231

A digital electronic circuit device comprises a plurality of circuit elements, a scan chain establishment element, and a unitary clock domain establishment element. The plurality of circuit elements define a plurality of clock domains, and circuit elements in each clock domain perform processing operations under control of a respective domain clock signal. The scan chain establishment element interconnects the circuit elements in a scan chain to facilitate loading and/or retrieval of a scan vector into and/or out of the digital circuit device. The unitary clock domain establishment element establishes a unitary clock domain for the circuit element when the scan chain establishment element is interconnecting the circuit elements in a scan chain. Thus, the scan vector will be loaded into or retrieved from the digital electronic circuit device using the single, unitary clock signal, thereby avoiding any necessity of using synchronizers or other elements for the scan chain which can complicate layout of the device.

48887129, Dec 19, 1989

Nov 4, 1987

7/117112

Anthony C. Barkans - Billerica MA
Brian D. Schroeder - Lowell MA
Thomas L. Durant - Billerica MA
Dorothy Gordon - Somerville MA
Jorge Lach - Burlington MA

Schlumberger Systems, Inc. - Sunnyvale CA

G06F 314
G06F 1572

364522

A system for clipping polygons representing three-dimensional objects to produce a representation of the portion of the objects in a desired viewing space is disclosed. A guardband space at least partially enclosing the viewing space is defined. The polygons are compared to the guardband space to determine which polygons intersect at least one of the guardband planes defining the guardband space. The intersecting polygons are also compared to the viewing space to determine if they intersect at least one of the viewing planes defining the viewing space. Only polygons intersecting both a viewing plane and a guardband plane are clipped.

49889850, Jan 29, 1991

Jul 24, 1989

7/384877

Anthony C. Barkans - Woburn MA
Jorge Lach - Arlington MA

Schlumberger Technology Corporation - Houston TX

G09G 530

340750

A three-dimensional frame-buffer memory organized into a series of planes each storing one bit representative of a pixel on the display can draw a figure onto one of the planes. The figure can then be copied to preselected ones of the other planes while the first plane is cleared. A bit block transfer can be performed from an "invisible" portion of the first plane to pre-selected ones of the other planes.

59533439, Sep 14, 1999

Nov 26, 1996

8/756657

Jorge E. Lach - Lexington MA

Sun Microsystems, Inc. - Palo Alto PA

H04L 1254

370428

A digital data transfer system comprises a source module and a destination module interconnected by an information transfer medium. The source module initiates a transfer operation in which it transfers a data item and an associated address over an information transfer medium. The address having an aperture identification portion that identifies one of a plurality of apertures. The destination module receives the data item and the associated address from the information transfer medium during the transfer operation, the destination module using the one of the plurality of apertures identified by the aperture identification portion to generate an aperture value for association with the data item. The source module can also initiate a retrieval operation, during which it transfers an address over the information transfer medium to retrieve previously transferred information. The address used during the retrieval operation also has an aperture identification portion that includes an aperture identification value that identifies one of a plurality of the apertures.