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John George Maltabes

from Hearne, TX
Age ~66

John Maltabes Phones & Addresses

  • 911 Anderson St, Hearne, TX 77859 (512) 636-2922
  • 4512 Eagle Feather Dr, Austin, TX 78735 (512) 892-2923 (512) 892-3121 (512) 892-5465
  • 1610 Gaylord Dr, Austin, TX 78728 (512) 989-8002
  • 1 Placid Dr, Schenectady, NY 12303
  • 3125 Tibbett Ave, Bronx, NY 10463 (718) 796-0647
  • Rochester, NY
  • Mendham, NJ
  • Taylor, TX
  • 4512 Eagle Feather Dr, Austin, TX 78735 (512) 636-2922

Work

Company: Hewlett packard labs - Palo Alto, CA Apr 2009 Position: Visiting scholar

Education

School / High School: Rochester Institute of Technology- Rochester, NY 1991 Specialities: Masters in Manufacturing Engineering

Emails

Resumes

Resumes

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John Maltabes Austin, TX

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Work:
Hewlett Packard Labs
Palo Alto, CA
Apr 2009 to May 2013
Visiting Scholar

Molecular Imprints Inc
Austin, TX
Oct 2006 to Dec 2008
CMOS Applications Manager - Senior Process Engineer

Photronics Incorporated
Austin, TX
Feb 2005 to Sep 2006
Imprint Template Product Manager - Principal Engineer

Freescale Semiconductor/Motorola
Austin, TX
1993 to 2004
Principal Staff Engineer - Gold Badge

International Business Machines
Burlington, VT
1982 to 1993
Senior Associate Engineer

Education:
Rochester Institute of Technology
Rochester, NY
1991 to 1992
Masters in Manufacturing Engineering

Rochester Institute of Technology
Rochester, NY
1977 to 1982
BS in Science and Instrumentation

Publications

Us Patents

Method Of Fabricating Semiconductor Devices With Contact Studs Formed Without Major Polishing Defects

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US Patent:
6486049, Nov 26, 2002
Filed:
Apr 30, 2001
Appl. No.:
09/845600
Inventors:
John Maltabes - Austin TX
Hans Zeindl - Dresden, DE
Assignee:
Motorola, Inc. - Schaumburg IL
Semiconductor 300 GmbH Co. KG - Dresden
Infineon Technologies AG - Munich
International Classification:
H01L 21283
US Classification:
438597, 438690
Abstract:
In a semiconductor device, a contact stud ( ) contacts a semiconductor substrate ( ); the stud is embedded in an insulating structure with a first insulating layer ( ) and a second insulating layer ( ). During manufacturing, (a) the first layer ( ) is provided above the substrate ( ); (b) a hole in the first layer ( ) exposes a portion of the upper surface of the substrate to receive the stud; (c) a contact material ( ) is provided at the top of the resulting structure; (d) a first chemical-mechanical polishing (CMP) removes the contact material from the surface of the first layer ( ) outside the hole; (e) residuals ( ) of the contact material are cleaned away from the upper surface; (f) the second insulating layer ( ) is provided at the surface of the resulting structure; (g) and further polishing is applied.

Wafer Processing Equipment And Method For Processing Wafers

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US Patent:
6491451, Dec 10, 2002
Filed:
Nov 3, 2000
Appl. No.:
09/706201
Inventors:
Timothy Stanley - Austin TX
John Maltabes - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G03D 500
US Classification:
396611, 118 52, 414935, 700218
Abstract:
A wafer processing equipment comprises a track ( ) for transporting wafers, a wafer launch station ( ) for launching wafers into a section of said track ( ), a first wafer processing tool ( ) for performing a first process to wafers in said section of said track ( ), a buffer ( ) for storing wafers processed by said first wafer processing tool ( ), a second wafer processing tool ( ) for performing a second process to wafers processed by said first wafer processing tool ( ), and control means ( ) for controlling said wafer launch station ( ) such that every wafer launched by said launch station ( ) is processed by said second processing tool ( ) within a predetermined time window.

Temperature-Controlled Chuck And Method For Controlling The Temperature Of A Substantially Flat Object

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US Patent:
6495802, Dec 17, 2002
Filed:
May 31, 2001
Appl. No.:
09/871854
Inventors:
John G. Maltabes - Austin TX
Alain B. Charles - Singapore, SG
Karl E. Mautz - Round Rock TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
C23C 1600
US Classification:
219390, 219405, 219411, 118724, 118725, 392416, 392418
Abstract:
The present invention generally relates to a method for controlling the temperature of a substantially flat object and to a temperature-controlled chuck comprising a chuck body ( ) having an object support side ( ) and a back side ( ). Said object support side ( ) holds a substantially flat object ( ) having a front side ( ) and a back side ( ) on said back side ( ) of said object ( ). A plurality of temperature sensing elements ( ) is distributed on said object support side ( ) to measure the temperature distribution of said flat object ( ). A plurality of individual temperature influencing elements ( ) is distributed on said object support side ( ) to face said back side ( ) of said flat object ( ), each of said temperature influencing elements ( ) being arranged to influence the temperature of a partial area of said objects back side ( ) as desired.

Method For Chemical Mechanical Polishing (Cmp) With Altering The Concentration Of Oxidizing Agent In Slurry

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US Patent:
6589099, Jul 8, 2003
Filed:
Jul 9, 2001
Appl. No.:
09/901365
Inventors:
John Maltabes - Austin TX
Karl Emerson Mautz - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
B24B 1900
US Classification:
451 41, 451 36, 451 11, 438692, 15634512, 15634516
Abstract:
Chemical mechanical polishing (CMP) a metal film ( ) at the surface of a substrate ( ), with mixing a slurry precursor ( ) with an oxidizing agent ( ) to provide a slurry ( ) with a predetermined agent concentration, and supplying the slurry to a CMP pad ( ) to polish the film at a predetermined polishing rate is modified by altering the agent concentration at the end of polishing. Since the polishing rate is reduced, endpointing is enhanced. The concentration is altered by adding further oxidizing or reducing agents.

Lithography Method For Forming Semiconductor Devices On A Wafer Utilizing Atomic Force Microscopy

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US Patent:
6620563, Sep 16, 2003
Filed:
Mar 8, 2001
Appl. No.:
09/801522
Inventors:
John George Maltabes - Austin TX
Alain Bernard Charles - Singapore, SG
Karl Emerson Mautz - Round Rock TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G03F 900
US Classification:
430 22, 430 30
Abstract:
A semiconductor device on a wafer is formed by lithography with the following steps of: coating ( ) a lithography resist onto said wafer in a coating means ( ), exposing ( ) said wafer to an irradiation through a reticle in an exposure tool ( ), stabilizing ( ) said lithography resist for activating chemical reaction and developing said lithography resist in said predetermined areas in a developer means ( ) so as to reveal a predetermined lithography resist pattern on the wafer surface, stabilizing ( ) the lithography resist in a stabilization means ( ) for strengthening said pattern on the wafer surface, performing ( ) a metrology inspection of said lithography resist pattern on said wafer surface in a metrology tool ( ), etching, wet processing or implanting ions ( ) into said wafer in a processing cell ( ), wherein said metrology inspection is performed by atomic force microscopy in a atomic force microscopy module ( ) immediately after developing and baking said lithography resist adjacent to said stabilization means ( ).

Semiconductor Structure And Method For Reducing Charge Damage

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US Patent:
6686254, Feb 3, 2004
Filed:
Apr 27, 2001
Appl. No.:
09/842453
Inventors:
Joseph Petrucci - New Milford CT
John Maltabes - Austin TX
Karl Mautz - Austin TX
Alain Charles - Singapore, SG
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2176
US Classification:
438401, 438400, 438694, 438597, 438622, 438669, 257356, 257362
Abstract:
A semiconductor method for reducing charge damage during plasma etch processing is disclosed. Structures ( ) for accumulating charge during plasma etch processing are provided on a semiconductor wafer ( ), the structures ( ) being electrically connected to device structures ( ).

Arrangement And Method For Transferring A Pattern From A Mask To A Wafer

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US Patent:
6737205, May 18, 2004
Filed:
Apr 30, 2002
Appl. No.:
10/135463
Inventors:
John George Maltabes - Austin TX
Alain Bernard Charles - Singapore, SG
Karl E. Mautz - Round Rock TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G03F 900
US Classification:
430 22, 430 5
Abstract:
An arrangement for transferring a pattern from a mask ( ) onto a wafer is provided. A product area ( ) of the mask ( ) is at least partly surrounded by a frame ( ) having an alignment mark area ( ). In order to avoid the need to produce a specific mask set for different alignment styles, the mask ( ) and the frame ( ) are designed as being separate units. Further, methods for transferring a pattern from a mask to a wafer are provided that employ a frame separated from a product area.

Continuously Adjustable Neutral Density Area Filter

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US Patent:
6744494, Jun 1, 2004
Filed:
Dec 7, 2001
Appl. No.:
10/012989
Inventors:
John Maltabes - Austin TX
Karl Mautz - Round Rock TX
Alain Charles - Maplewoods, SG
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
G03B 2772
US Classification:
355 71, 355 53
Abstract:
An apparatus for compensating light exposure on different, subsequently irradiated target areas ( ) in a photosensitive medium ( ) on a semiconductor wafer ( ). In order to improve exposure dose uniformity the apparatus comprises a mask filter ( ) with a plurality of oblong transparent ( ) and oblong opaque elements ( ) inserted between a light source ( ) and said photosensitive medium ( ) so that light ( ) traverses through said plurality of transparent elements ( ) to expose the photosensitive medium. Each of said plurality of oblong opaque elements ( ) is rotatable around a longitudinal axis ( ) so as to define the area masked by the projection of the opaque element on the photosensitive medium and to continuously adjust a ratio between irradiated and non-irradiated areas on the photosensitive medium.
John George Maltabes from Hearne, TX, age ~66 Get Report