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John K Kibarian

from Los Altos Hills, CA
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Also known as:
John Kachig Kibarian
Phone and address:
23351 Camino Hermoso Dr, Los Altos, CA 94024
Related to:
Xiyong Chen, 48Hachik K Chilingirian, 71Joe KibarianJohanna A Chilingirian, 63Yu ChenWen Shuh Chen, 90Wen Shen Chen
Connected to:
Glenda G Kibat, 69Priscilla W Kibathi, 56Corydon Kibbe, 51Jeanne Kibbe, 99Mary A Kibbe, 44Nathaniel Kibbe, 84Patricia M Kibbe, 59Rachael A Kibbe, 61Shannon R Kibbe, 41Starla R Kibbe, 38

John Kibarian Phones & Addresses

  • 23351 Camino Hermoso Dr, Los Altos, CA 94024
  • Los Altos Hills, CA

Business Records

Name / Title
Company / Classification
Phones & Addresses
John Kibarian
Director
Eda Consortium Inc
Business Association · Business Associations
3081 Zanker Rd, San Jose, CA 95134
111 W Saint John St, San Jose, CA 95113
(408) 287-3322, (408) 283-5283
John K. Kibarian
President
PDF ACQUISITION CORP
333 W San Carlos St STE 700, San Jose, CA 95110

Publications

Us Patents

System And Method For Product Yield Prediction

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US Patent:
6901564, May 31, 2005
Filed:
Jul 18, 2002
Appl. No.:
10/200045
Inventors:
Brian E. Stine - Los Altos Hills CA, US
Christopher Hess - San Ramon CA, US
John Kibarian - Los Altos Hills CA, US
Kimon Michaels - San Jose CA, US
Joseph C. Davis - Allen TX, US
Purnendu K. Mozumder - Plano TX, US
Sherry F. Lee - San Jose CA, US
Larg H. Weiland - San Ramon CA, US
Dennis J. Ciplickas - San Jose CA, US
David M. Stashower - Los Gatos CA, US
Assignee:
PDF Solutions, Inc. - San Jose CA
International Classification:
G06F017/50
G06F019/00
US Classification:
716 4, 700121
Abstract:
A yield for an integrated circuit is predicted by processing a wafer to have a portion fabricated with at least one layout attribute of the integrated circuit. The portion of the wafer is analyzed to determine an actual yield associated with the at least one layout attribute. A systematic yield associated with the at least one layout attribute is determined based on the actual yield and a predicted yield associated with the at least one layout attribute. The predicted yield assumes that random defects are the only yield loss mechanism. A yield of an actual or proprosed product layout is predicted for the integrated circuit based on the systematic yield.

System And Method For Product Yield Prediction

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US Patent:
7174521, Feb 6, 2007
Filed:
Mar 10, 2005
Appl. No.:
11/078630
Inventors:
Brian E. Stine - Los Altos CA, US
Christopher Hess - San Ramon CA, US
John Kibarian - Los Altos Hills CA, US
Kimon Michaels - San Jose CA, US
Joseph C. Davis - Allen TX, US
Purnendu K. Mozumder - Plano TX, US
Sherry F. Lee - San Jose CA, US
Larg H. Weiland - San Ramon CA, US
Dennis J. Ciplickas - San Jose CA, US
David M. Stashower - Los Gatos CA, US
Assignee:
PDF Solutions, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 4, 703 2
Abstract:
A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

System And Method For Product Yield Prediction

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US Patent:
7356800, Apr 8, 2008
Filed:
Aug 10, 2006
Appl. No.:
11/503323
Inventors:
Brian E. Stine - Los Altos CA, US
Christopher Hess - San Ramon CA, US
John Kibarian - Los Altos Hills CA, US
Kimon Michaels - San Jose CA, US
Joseph C. Davis - Allen TX, US
Purnendu K. Mozumder - Plano TX, US
Sherry F. Lee - San Jose CA, US
Larg H. Weiland - San Ramon CA, US
Dennis J. Ciplickas - San Jose CA, US
David M. Stashower - Los Gatos CA, US
Assignee:
PDF Solutions, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 21, 716 4, 716 19
Abstract:
A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

System And Method For Product Yield Prediction

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US Patent:
7373625, May 13, 2008
Filed:
Aug 10, 2006
Appl. No.:
11/503433
Inventors:
Brian E. Stine - Los Altos CA, US
Christopher Hess - San Ramon CA, US
John Kibarian - Los Altos Hills CA, US
Kimon Michaels - San Jose CA, US
Joseph C. Davis - Allen TX, US
Purnendu K. Mozumder - Plano TX, US
Sherry F. Lee - San Jose CA, US
Larg H. Weiland - San Ramon CA, US
Dennis J. Ciplickas - San Jose CA, US
David M. Stashower - Los Gatos CA, US
Assignee:
PDF Solutions, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 4, 716 19, 716 21
Abstract:
A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

System And Method For Product Yield Prediction

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US Patent:
7673262, Mar 2, 2010
Filed:
May 13, 2008
Appl. No.:
12/119862
Inventors:
Brian E. Stine - Los Altos Hills CA, US
Christopher Hess - San Ramon CA, US
John Kibarian - Los Altos Hills CA, US
Kimon Michaels - San Jose CA, US
Joseph C. Davis - Allen TX, US
Purnendu K. Mozumder - Plano TX, US
Sherry F. Lee - San Jose CA, US
Larg H. Weiland - San Ramon CA, US
Dennis J. Ciplickas - San Jose CA, US
David M. Stashower - Los Gatos CA, US
Assignee:
PDF Solutions, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 4, 716 21
Abstract:
A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.

Reusable Test Chip For Inline Probing Of Three Dimensionally Arranged Experiments

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US Patent:
8362480, Jan 29, 2013
Filed:
Sep 25, 2007
Appl. No.:
11/903943
Inventors:
Christopher Hess - San Carlos CA, US
John Kibarian - Los Altos Hills CA, US
Amit Joag - Sunnyvale CA, US
Abdul Mobeen Mohammed - Santa Clara CA, US
Ben Shieh - Sunnyvale CA, US
David Stashower - San Jose CA, US
Assignee:
PDF Solutions, Inc. - San Jose CA
International Classification:
H01L 29/10
US Classification:
257 48, 257E23179, 257E21521, 257E21524
Abstract:
A Characterization Vehicle (CV) and a method for forming it which yields a gain in efficiency for IC yield ramp improvements by enabling faster learning cycles and diagnosis while reducing costs. A plurality of SF experiments are combined into a single full flow mask set with many inline testing points. Smaller pads are arranged in a way supporting testing of interleaved pad frames, parallel testing, and the usage of stacked test structures, or Devices Under Test (DUT's).

Integrated Circuit Design To Optimize Manufacturability

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US Patent:
20060253810, Nov 9, 2006
Filed:
Sep 16, 2003
Appl. No.:
10/572151
Inventors:
Carlo Guardiani - Verona, IT
Nicola Dragone - Vobarno, IT
John Kibarian - Los Altos CA, US
Enrico Malavasi - Mountain View CA, US
Rijko Radocic - San Diego CA, US
Andrzej Strojwas - Pittsburgh PA, US
International Classification:
G06F 17/50
US Classification:
716004000
Abstract:
Library design elements () are analyzed for manufacturability to be used in designing an IC chip to be manufactured using a particular manufacturing process. The library design elements from a library are obtained. Manufacturability attributes () of the library design elements are determined for the particular manufacturing process, where manufacturability attributes include yield-related attributes. Library views () with manufacturability attributes for the library design elements are then generated, which are utilizing by an electronic design automation (EDA) tool.

System And Method For Product Yield Prediction Using A Logic Characterization Vehicle

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US Patent:
6834375, Dec 21, 2004
Filed:
Sep 16, 2002
Appl. No.:
10/130380
Inventors:
Brian E. Stine - Los Altos Hills CA
Christopher Hess - San Ramon CA
Larg H. Weiland - San Ramon CA
Dennis J. Ciplickas - San Jose CA
John Kibarian - Los Altos Hills CA
Assignee:
PDF Solutions, Inc. - San Jose CA
International Classification:
G06F 1750
US Classification:
716 2, 716 4
Abstract:
A characterization vehicle includes at least one combinatorial logic circuit element, and a control circuit that controls the combinatorial logic circuit element. The control circuit includes an input mechanism for inputting a test pattern of signals into the combinatorial logic circuit element. An output mechanism stores an output pattern that is output by the combinatorial logic circuit element based on the test pattern. A ring bus connects the output means to the input means so as to cause oscillation. A counter counts a frequency of the oscillation, thereby to measure performance of the combinatorial logic circuit element.
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John K Kibarian from Los Altos Hills, CA Get Report