John A Iacoponi

6340633, Jan 22, 2002

Mar 26, 1999

09/276839

Sergey D. Lopatin - Santa Clara CA
John A. Iacoponi - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 214763

438625, 438678, 438687

A method is provided for forming conductive layers in semiconductor channels and vias by using ramped current densities for the electroplating process. The lower density currents are used initially to deposit a fine grain conductive layer in the vias and then higher densities are used to deposit a large grain conductive layer in the channel.

6346472, Feb 12, 2002

Feb 16, 2001

09/784022

Sergey D. Lopatin - Santa Clara CA
John A. Iacoponi - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 214763

438627, 438685, 438687, 438648, 438653

A semiconductor metalization barrier, and manufacturing method therefor, is provided which is deposited from an aqueous solution containing the Period 4 transition metals of chromium, nickel, and copper deposited on a palladium-activated copper bonding pad.

6413846, Jul 2, 2002

Nov 14, 2000

09/712501

Paul R. Besser - Austin TX
Errol Todd Ryan - Austin TX
Frederick N. Hause - Austin TX
Frank Mauersberger - Austin TX
William S. Brennan - Austin TX
John A. Iacoponi - Austin TX
Peter J. Beckage - Austin TX

Advanced Micro Devices, Inc. - Austin TX

H01L 2144

438597, 438634, 438629, 438970

A method of forming conductive contacts or an integrated circuit device is disclosed herein. In one embodiment, the method comprises forming a transistor above a semiconducting substrate, and forming a first layer comprised of an orthosilicate glass material above the transistor and the substrate. The method further comprises forming a second layer comprised of an insulating material above the first layer, and performing at least one etching process to define an opening in the second layer for a conductive contact to be formed therein, wherein the first layer comprised of an orthosilicate glass material acts as an etch stop layer during the etching of the opening in the second layer.

6448099, Sep 10, 2002

Nov 28, 2000

09/723485

John A. Iacoponi - Austin TX
Tom Spikes, Jr. - Round Rock TX
John Miethke - Austin TX

Advanced Micro Devices, Inc. - Austin TX

H01L 3126

438 17, 438 14

A method is used to test a semiconductor wafer for misaligned layers formed therein. The method comprises forming a plurality of electrically conductive connections on a surface of the semiconductor wafer. A portion of the electrically conductive connections are coupled to a voltage supply. Thereafter, a voltage contrast analysis of the surface of the semiconductor wafer is performed, and a first pattern of the plurality of electrically conductive connections coupled to the voltage supply is determined from the voltage contrast analysis. The method further comprises comparing the first pattern to a desired pattern, and indicating an error in response to the first pattern differing from the desired pattern.

6468889, Oct 22, 2002

Aug 8, 2000

09/633931

John A. Iacoponi - Austin TX
John C. Miethke - Austin TX

Advanced Micro Devices, Inc. - Austin TX

H01L 2144

438597, 438622, 438667, 438675

A contact formed from the backside of an integrated circuit device includes a first conductive layer on a first surface of the integrated circuit device and a second conductive layer on a second surface of the device. The two conductive layers are coupled by way of an opening through the semiconductor substrate separating the two conductive layers. A method for making the backside contact comprises forming the first conductive layer, forming an opening through the semiconductor substrate to expose at least a portion of the underside of the first conductive layer, then filling the opening with a conductive material to provide an electrical contact to the first conductive layer from the backside of the integrated circuit device.

6489240, Dec 3, 2002

May 31, 2001

09/871305

John A. Iacoponi - Austin TX
Paul R. Besser - Sunnyvale CA
Frederick N. Hause - Austin TX
Frank Mauersberger - Radebeul, DE
Errol Todd Ryan - Austin TX
William S. Brennan - Austin TX
Peter J. Beckage - Austin TX

Advanced Micro Devices, Inc. - Austin TX

H01L 214763

438687, 438633, 438692

A method for forming a semiconductor having improved copper interconnects is provided. The method comprises forming a first dielectric layer above a first structure layer. Thereafter, a first opening is formed in the first dielectric layer, and a first copper layer is formed above the first dielectric layer and in the first opening. A portion of the first copper layer outside of the opening is removed. A surface portion of the first copper layer is also removed from within the opening, and a second layer of copper is formed above the first layer of copper, replacing the removed surface portion.

6489683, Dec 3, 2002

Oct 10, 2001

09/975032

Sergey D. Lopatin - Santa Clara CA
John A. Iacoponi - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 2348

257750, 257753, 257762, 257765

A method is provided for forming conductive layers in semiconductor channels and vias by using ramped current densities for the electroplating process. The lower density currents are used initially to deposit a fine grain conductive layer in the vias and then higher densities are used to deposit a large grain conductive layer in the channel.

6514858, Feb 4, 2003

Apr 9, 2001

09/829202

Frederick N. Hause - Austin TX
Paul R. Besser - Austin TX
Frank Mauersberger - Radebeul, DE
Errol Todd Ryan - Austin TX
William S. Brennan - Austin TX
John A. Iacoponi - Austin TX
Peter J. Beckage - Austin TX

Advanced Micro Devices, Inc. - Austin TX

H01L 214763

438640, 438638, 438639, 438701, 216 59, 216 84

A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region. Thus, as the process layer and interconnects are removed by the polishing process, the distance X increases, indicating the depth of the polishing process.