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John J D'Urso

from Chandler, AZ
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John D'Urso Phones & Addresses

  • Chandler, AZ

Resumes

Resumes

John D'Urso Photo 1

Account Executive At Intercall

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Location:
United States
John D'Urso Photo 2

John D'urso

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Location:
United States
John D'Urso Photo 3

John D'urso

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Location:
United States

Publications

Us Patents

Cladded Conductor For Use In A Magnetoelectronics Device And Method For Fabricating The Same

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US Patent:
6885074, Apr 26, 2005
Filed:
Nov 27, 2002
Appl. No.:
10/306250
Inventors:
Mark A. Durlam - Chandler AZ, US
Jeffrey H. Baker - Chandler AZ, US
Brian R. Butcher - Gilbert AZ, US
Mark F. Deherrera - Tempe AZ, US
John J. D'Urso - Chandler AZ, US
Earl D. Fuchs - Phoenix AZ, US
Gregory W. Grynkewich - Gilbert AZ, US
Kelly W. Kyler - Mesa AZ, US
Jaynal A. Molla - Gilbert AZ, US
J. Jack Ren - Phoenix AZ, US
Nicholas D. Rizzo - Gilbert AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L029/82
H01L027/14
US Classification:
257422, 257252
Abstract:
A method for fabricating a cladded conductor () for use in a magnetoelectronics device is provided. The method includes providing a substrate () and forming a conductive barrier layer () overlying the substrate (). A dielectric layer () is formed overlying the conductive barrier layer () and a conducting line () is formed within a portion of the dielectric layer (). The dielectric layer () is removed and a flux concentrator () is formed overlying the conducting line ().

Method Of Applying Cladding Material On Conductive Lines Of Mram Devices

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US Patent:
6927072, Aug 9, 2005
Filed:
Mar 8, 2002
Appl. No.:
10/093909
Inventors:
Jaynal A. Molla - Gilbert AZ, US
John D'Urso - Chandler AZ, US
Kelly Kyler - Mesa AZ, US
Bradley N. Engel - Chandler AZ, US
Gregory W. Grynkewich - Gilbert AZ, US
Nicholas D. Rizzo - Gilbert AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L021/00
US Classification:
438 3, 438612, 438613, 438614, 257295, 365158, 365171, 365172, 365173
Abstract:
A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.

Cladded Conductor For Use In A Magnetoelectronics Device And Method For Fabricating The Same

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US Patent:
7105363, Sep 12, 2006
Filed:
Mar 16, 2005
Appl. No.:
11/082617
Inventors:
Mark A. Durlam - Chandler AZ, US
Jeffrey H. Baker - Chandler AZ, US
Brian R. Butcher - Gilbert AZ, US
Mark F. Deherrera - Tempe AZ, US
John J. D'Urso - Chandler AZ, US
Earl D. Fuchs - Phoenix AZ, US
Gregory W. Grynkewich - Gilbert AZ, US
Kelly W. Kyler - Mesa AZ, US
Jaynal A. Molla - Gilbert AZ, US
J. Jack Ren - Phoenix AZ, US
Nicholas D. Rizzo - Gilbert AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21/00
US Classification:
438 3, 438652, 438653, 438666, 257E21002
Abstract:
A method for fabricating a cladded conductor () for use in a magnetoelectronics device is provided. The method includes providing a substrate () and forming a conductive barrier layer () overlying the substrate (). A dielectric layer () is formed overlying the conductive barrier layer () and a conducting line () is formed within a portion of the dielectric layer (). The dielectric layer () is removed and a flux concentrator () is formed overlying the conducting line ().

Method Of Applying Cladding Material On Conductive Lines Of Mram Devices

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US Patent:
7402529, Jul 22, 2008
Filed:
May 26, 2005
Appl. No.:
11/139143
Inventors:
Jaynal A. Molla - Gilbert AZ, US
John D'Urso - Chandler AZ, US
Kelly Kyler - Mesa AZ, US
Bradley N. Engel - Chandler AZ, US
Gregory W. Grynkewich - Gilbert AZ, US
Nicholas D. Rizzo - Gilbert AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21/302
US Classification:
438745, 216 18, 216 22, 216 38, 257108, 257295, 257414, 257421, 365157, 365158, 365171, 365173, 438 42, 438692, 438723, 438724, 438741, 438754
Abstract:
A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.

Smudge Removal From Electronic Device Displays

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US Patent:
7729106, Jun 1, 2010
Filed:
Mar 29, 2007
Appl. No.:
11/693445
Inventors:
John J. D'Urso - Chandler AZ, US
Steven M. Smith - Gilbert AZ, US
Steven A. Voight - Gilbert AZ, US
Steve X. Dai - Gilbert AZ, US
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H05K 5/00
H04M 1/00
US Classification:
36167901, 134 32, 34038471, 455567
Abstract:
An apparatus and method is provided for removing smudges () including oils and dust from portable electronic displays. The apparatus comprises a display device () positioned within a housing (), comprising a transparent cover () having a surface () viewable through an opening in the housing () and a susceptibility to receiving contaminants (). A vibration device () is positioned against the transparent cover () to provide motion () in a direction parallel to the surface, thereby causing the contaminants to move () across the surface (). The contaminants () may then be hidden by the housing () or ejected by a motion () perpendicular to the surface by another vibrating device (). Electronic circuitry () is provided for activating the vibration device () either during normal operation of the electronic device or as selected by the user.

Method Of Fabricating A Self-Aligned Via Contact For A Magnetic Memory Element

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US Patent:
20030175997, Sep 18, 2003
Filed:
Mar 12, 2002
Appl. No.:
10/095816
Inventors:
Kelly Kyler - Mesa AZ, US
Saied Tehrani - Tempe AZ, US
John D'urso - Chandler AZ, US
Gregory Grynkewich - Gilbert AZ, US
Mark Durlam - Chandler AZ, US
Brian Butcher - Gilbert AZ, US
International Classification:
H01L021/00
H01L021/44
H01L021/302
US Classification:
438/003000, 438/692000
Abstract:
A method of fabricating a magnetoresistive random access memory device comprising the steps of providing a substrate, forming a conductive layer positioned on the substrate, forming a magnetoresistive random access memory device positioned on conductive layer, forming a metal cap on the magnetoresistive random access memory device, and electroless plating a bump metal layer on the metal cap. The bump metal layer acts as a self-aligned via for a bit line subsequently formed thereon.

Method Of Forming A Flux Concentrating Layer Of A Magnetic Device

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US Patent:
20040175845, Sep 9, 2004
Filed:
Mar 3, 2003
Appl. No.:
10/377952
Inventors:
Jaynal Molla - Gilbert AZ, US
John D'Urso - Chandler AZ, US
J. Ren - Phoenix AZ, US
International Classification:
H01L021/00
US Classification:
438/003000
Abstract:
A method of forming a magnetic device, especially the digit line of a magnetic random access memory (MRAM) device is disclosed. The digit line includes a stack of materials that includes a barrier layer, a seed layer and a soft magnetic layer that is electrochemically deposited. Preferably, the barrier layer and the seed layer are formed by physical vapor deposition (PVD) and the soft magnetic layer is formed by electroless plating. In one embodiment, the barrier layer includes tantalum, the seed layer includes ruthenium and the soft magnetic layer includes nickel and iron.

Compositions And Methods For The Electroless Deposition Of Nife On A Work Piece

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US Patent:
20050095855, May 5, 2005
Filed:
Nov 5, 2003
Appl. No.:
10/702909
Inventors:
John D'urso - Chandler AZ, US
Jaynal Molla - Gilbert AZ, US
Kelly Kyler - Mesa AZ, US
International Classification:
B05D005/12
C23C018/34
C23C018/36
H01L021/44
US Classification:
438678000, 427443100, 427058000, 106001220, 106001270
Abstract:
Methods and compositions are provided for the electroless deposition of NiFe on a work piece. A deposition solution for use in electroless deposition of NiFe on a work piece is formed from a nickel ion source, a ferrous iron source, a complexing agent, a reducing agent, and a pH adjusting agent. The deposition solution is substantially free from alkali metal ions. A method for fabricating a flux concentrating system for use in a magnetoelectronics device begins by providing a work piece and forming an insulating material layer overlying the work piece. A trench is formed in an insulating layer and a barrier layer is deposited within the trench. A NiFe cladding layer is deposited overlying the barrier layer. After depositing the NiFe cladding layer, the insulating material layer proximate to the trench has a concentration of alkali metal ions less than about 1×10atoms/cm.
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John J D'Urso from Chandler, AZ Get Report