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Joel Z Apisdorf

from Reston, VA
Age ~60
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Also known as:
Joel Joel, Joel F
Phone and address:
12205 Nutmeg Ln, Herndon, VA 20191
(703) 860-0299
Related to:
Sharon M Apisdorf, 62Joshua M Apisdorf, 28Lynda J Rosenkrantz, 53Herb Rosenkrantz, 90Nadeen K Apisdorf, 60Anita J Apisdorf, 29Rodolfo Zubiate, 72Veronica C Zubiate, 46Dorothy RosenkrantzJudith C Apisdorf, 87Dorothy P Rosenkrantz
Connected to:
Stefan J Apitz, 60Charles O Apiyo, 62Jared R Apjoke, 47Amy Apke, 54Eileen F Apke, 77Jennifer L Apker, 50Kristy N Apker, 33Lesley A Apker, 59Virginia L Apker, 88

Joel Apisdorf Phones & Addresses

  • 12205 Nutmeg Ln, Reston, VA 20191 (703) 860-0299
  • Falls Church, VA
  • Vienna, VA
  • Gaithersburg, MD
  • Miami, FL
  • Dunnellon, FL
  • 12205 Nutmeg Ln, Reston, VA 20191 (703) 582-4460

Work

Company: Trident systems, inc Mar 2007 Position: Principal network/digital engineer

Education

School / High School: Case Western Reserve University- Cleveland, OH Jan 1987 Specialities: BS in Computer Engineering

Skills

10 patents granted • 1 paper published

Industries

Research

Resumes

Resumes

Joel Apisdorf Photo 1

Principal Hw Engineer

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Location:
Reston, VA
Industry:
Research
Work:
Netscout
Principal Hw Engineer
Trident Systems Mar 2007 - Feb 2012
Principal Network and Digital Engineer
Freescale Semiconductor Mar 2001 - Feb 2007
Senior Principal Engineer
Acorn Networks Feb 2000 - Mar 2001
Network Processor Architect
Worldcom Feb 1995 - Jan 2000
Senior Engineer
Education:
Case Western Reserve University 1982 - 1984
Skills:
Computer Hardware
Architecture
Cross Functional Team Leadership
Information Security
Research and Development
Agile Methodologies
Security
Radio Frequency
Radar
Network Architecture
Semiconductors
Digital Signal Processing
Government Contracting
C
Debugging
Embedded Software
Embedded Systems
Fpga
Hardware Architecture
Integration
Multithreading
Programming
System Architecture
System Design
Software Development
Program Management
Systems Design
Systems Engineering
Joel Apisdorf Photo 2

Joel Apisdorf Reston, VA

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Work:
Trident Systems, Inc

Mar 2007 to 2000
Principal Network/Digital Engineer
Freescale Semiconductor
Vienna, VA
Mar 2001 to Feb 2007
Sr. Principal Engineer
Acorn Networks
Reston, VA
Feb 2000 to Mar 2001
Sr. Engineer
MCI Worldcom
Ashburn, VA
Feb 1995 to Jan 2000
Consultant
Cable & Wireless Communications
Vienna, VA
1992 to Feb 1995
Consultant
GTE Government Information Services
Reston, VA
Oct 1990 to 1992
Consultant
IBM Corporation
Bethesda, MD
Mar 1990 to Oct 1990
Consultant
IBM Corporation
Boca Raton, FL
May 1989 to Apr 1990
Consultant
Data Access Corporation
Miami, FL
Jul 1985 to May 1989
Research & Development
Data Access Corporation
Miami, FL
Jul 1985 to Sep 1987
Technical Services
Self-employed
Miami, FL
Nov 1984 to Jul 1985
Consultant
AANI
Miami, FL
May 1984 to Nov 1984
Assistant System Operator
Education:
Case Western Reserve University
Cleveland, OH
Jan 1987
BS in Computer Engineering
Miami Sunset Sr. High
Miami, FL
Jan 1979 to Jan 1982
High School in general
Miami-Dade Community College
Miami, FL
Jan 1977 to Jan 1982
misc classes in Computer Science
Skills:
10 patents granted, 1 paper published

Publications

Us Patents

Method And Apparatus For Performing Error Checking In A Network

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US Patent:
6671832, Dec 30, 2003
Filed:
Dec 21, 1999
Appl. No.:
09/468462
Inventors:
Joel Z. Apisdorf - Reston VA
Assignee:
WorldCom, Inc. - Clinton MS
International Classification:
G06F 1108
US Classification:
714 52, 714758
Abstract:
A system and method for checking for data transmission errors in a network includes a cyclic redundancy code (CRC) generator and a processing device. The CRC generator receives a stream of data representing cells in a packet of data. The CRC generator generates a CRC value for each cell and transmits the CRC value to a processing device. The processing device combines the cell CRC values to generate a CRC for a packet of data. The processing device then compares the packet CRC to an expected value to determine whether an error occurred in the data transmission.

System And Method For Instruction-Level Parallelism In A Programmable Multiple Network Processor Environment

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US Patent:
6950927, Sep 27, 2005
Filed:
Apr 13, 2001
Appl. No.:
09/833580
Inventors:
Joel Zvi Apisdorf - Reston VA, US
Sam Brandon Sandbote - Reston VA, US
Assignee:
The United States of America as represented by the Secretary of the Navy - Washington DC
International Classification:
G06F009/00
US Classification:
712216, 712235
Abstract:
A system and method process data elements with instruction-level parallelism. An instruction buffer holds a first instruction and a second instruction, the first instruction being associated with a first thread, and the second instruction being associated with a second thread. A dependency counter counts satisfaction of dependencies of instructions of the second thread on instructions of the first thread. An instruction control unit is coupled to the instruction buffer and the dependency counter, the instruction control unit increments and decrements the dependency counter according to dependency information included in instructions. An execution switch is coupled to the instruction control unit and the instruction buffer, and the execution switch routes instructions to instruction execution units.

System And Method For Data Forwarding In A Programmable Multiple Network Processor Environment

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US Patent:
6968447, Nov 22, 2005
Filed:
Apr 13, 2001
Appl. No.:
09/833578
Inventors:
Joel Zvi Apisdorf - Reston VA, US
Sam Brandon Sandbote - Reston VA, US
Michael Daniel Poole - Reston VA, US
Assignee:
The United States of America as represented by the Secretary of the Navy - Washington DC
International Classification:
G06F013/00
US Classification:
712235, 712 22
Abstract:
A system and method forward data between processing elements. A first processing element includes an address register that stores a first memory address. A forwarding storage element is coupled to the first processing element. A second processing element, coupled to the forwarding storage element, transmits a second memory address to the forwarding storage element. The forwarding storage transmits the second memory address to the first processing element, and the first processing element compares the second memory address with the first memory address.

System And Method For Processing Overlapping Tasks In A Programmable Network Processor Environment

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US Patent:
6978459, Dec 20, 2005
Filed:
Apr 13, 2001
Appl. No.:
09/833581
Inventors:
Jack Bonnell Dennis - Belmont MA, US
Joel Zvi Apisdorf - Reston VA, US
Sam Brandon Sandbote - Reston VA, US
Assignee:
The United States of America as represented by the Secretary of the Navy - Washington DC
International Classification:
G06F009/46
US Classification:
718100, 718102
Abstract:
A system and method process data elements on multiple processing elements. A first processing element processes a task. A second processing element, coupled to the first processing element, is associated with a task. The first processing element sends a critical-section end signal to the second processing element while processing the task at the first processing element. The second processing element resumes the task in response to receiving the critical-section end signal.

Method Of Operating A Media Access Controller

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US Patent:
7280518, Oct 9, 2007
Filed:
Oct 3, 2002
Appl. No.:
10/262946
Inventors:
Sergio T. Montano - Vienna VA, US
William M. Shvodian - McLean VA, US
Knut T. Odman - Vienna VA, US
Russell G. Dowe - Vienna VA, US
Joel Z. Apisdorf - Reston VA, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H04B 7/212
US Classification:
370338, 370443, 370458, 370462
Abstract:
A method is provided for a remote device to monitor and communicate with a wireless network using cyclic beacons. The remote device receives a beacon, which beacon includes beacon information that defines a superframe. From the beacon information, the remote device determines whether the received beacon and the associated superframe are assigned to a network device or are unassigned. By receiving as many beacons as there are allowable devices in the network, the remote device can determine if the network is full. If the remote device runs through all of the beacons and all indicate that their associated superframes are assigned, then the remote device determines that the network is full and performs a network-full function. If the remote device receives a beacon that indicates that its associated superframe is unassigned, it determines that the network is not full and performs an association request during the unassigned superframe.

Method Of Transmitting And Receiving Data

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US Patent:
7548561, Jun 16, 2009
Filed:
May 13, 2005
Appl. No.:
11/128267
Inventors:
William M. Shvodian - McLean VA, US
Matthew L. Welborn - Vienna VA, US
Joel Z. Apisdorf - Reston VA, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H04J 3/24
US Classification:
370473, 370235
Abstract:
A method is provided for operating a transceiver that comprises: transmitting a preamble; transmitting an outer header identifying parameters of an outer payload, after transmitting the preamble; and transmitting the outer payload after transmitting the outer header. The transmitting of the outer payload includes: transmitting an inner header identifying parameters of an inner payload; transmitting an inner payload after transmitting the inner header; and repeating the transmitting of the inner header and the transmitting of the inner payload a plurality of times. A corresponding method of operating a receiver functions by receiving each of these transmitted elements.

Method For Sharing Bandwidth Using Reduced Duty Cycle Signals And Media Access Control

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US Patent:
7570627, Aug 4, 2009
Filed:
May 13, 2005
Appl. No.:
11/128269
Inventors:
Matthew L. Welborn - Vienna VA, US
William M. Shvodian - McLean VA, US
Joel Z. Apisdorf - Reston VA, US
Timothy R. Miller - Arlington VA, US
John W. McCorkle - Vienna VA, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H04J 3/00
H04B 7/212
H04W 4/00
H04J 3/24
H01Q 11/12
H04B 1/04
US Classification:
370345, 370347, 370329, 370474, 455522, 4551271
Abstract:
A method is provided for transmitting data. A first device generates a first signal having a first duty cycle, comprising a first gated-on portion and a first gated-off portion in a time slot; and a second device generates a second signal having second duty cycle, comprising a second gated-on portion and a second gated-off portion in the same time slot. The first gated-on portion is generated during a first segment of the time slot and the first gated-off portion is generated during a second segment of the time slot, while the second gated-on portion is generated during the second segment and the second gated-off portion is generated during the first segment. Media access control (MAC) can be used to further define positions within time slots and provide error correction, power control, and the like. A preamble can be transmitted at an increased power level to facilitate acquisition.

System And Method For Translucent Bridging

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US Patent:
7916736, Mar 29, 2011
Filed:
Sep 29, 2006
Appl. No.:
11/529305
Inventors:
William M. Shvodian - McLean VA, US
Joel Z. Apisdorf - Reston VA, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H04L 12/28
US Classification:
3703955, 370389, 370392
Abstract:
A network bridge () is provided, comprising: a local interface () configured to transmit and receive local signals in a local network (); a bridging interface () configured to transmit and receive bridging signals in a bridging network (); a control circuit () configured to pass outgoing local data packets from the local network to the bridging network and to pass incoming bridging payloads from the bridging network to the local network; and an address translation circuit () configured to provide the control circuit with address translation data identifying a correspondence between local packet addresses and global packet addresses. The control circuit translates outgoing local addresses to outgoing global addresses (), and the control circuit translates incoming global addresses to incoming local addresses (), based on the address translation data.
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Joel Z Apisdorf from Reston, VA, age ~60 Get Report