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Joachim Nuetzel Phones & Addresses

  • Fishkill, NY
  • Woronoco, MA

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Company: Joachim nuetzel Address: 24 Loudon Dr Apt 3B, Fishkill, NY 12524 Position: President Industries: Labor Unions and Similar Labor Organizations

Business Records

Name / Title
Company / Classification
Phones & Addresses
Joachim Nuetzel
President
Joachim Nuetzel
Labor Unions and Similar Labor Organizations
24 Loudon Dr Apt 3B, Fishkill, NY 12524
Joachim Nuetzel
President
Joachim Nuetzel
Labor Unions and Similar Labor Organizations
24 Loudon Dr Apt 3B, Fishkill, NY 12524

Publications

Us Patents

Metal Hard Mask For Ild Rie Processing Of Semiconductor Memory Devices To Prevent Oxidation Of Conductive Lines

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US Patent:
6440753, Aug 27, 2002
Filed:
Apr 2, 2001
Appl. No.:
09/824596
Inventors:
Xian J. Ning - Mohegan Lake NY
Joachim Nuetzel - Fishkill NY
Assignee:
Infineon Technologies North America Corp. - San Jose CA
International Classification:
H01L 21467
US Classification:
438 3, 438637, 438736, 438737, 438945
Abstract:
A method of patterning conductive lines ( ) of a memory array integrated circuit ( ) using a hard mask ( ) and reactive ion etching (RIE). Using a hard mask ( ) prevents oxidation of underlying conductive lines ( ).

Recessed Metal Lines For Protective Enclosure In Integrated Circuits

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US Patent:
6812141, Nov 2, 2004
Filed:
Jul 1, 2003
Appl. No.:
10/610609
Inventors:
Michael C. Gaidis - Wappingers Falls NY
Joachim Nuetzel - Fishkill NY
Walter Glashauser - Ringstrasse,
Eugene OSullivan - Nyack NY
Gregory Costrini - Hopewell Junction NY
Stephen L. Brown - Carmel NY
Frank Findeis - Hopewell Junction NY
Chanro Park - Fishkill NY
Assignee:
Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY
International Classification:
H01L 214763
US Classification:
438637, 438745
Abstract:
Encapsulating areas of metallization in a liner material, such as Tantalum, Tantalum Nitride, Silicon Carbide allows aggressive or harsh processing steps to be used. These aggresive processing steps offer the possibility of fabricating new device architectures. In addition, by encapsulating the areas of metallization, metal ion migration and electromigration can be prevented. Further, the encapsulated areas of metallization can serve as a self-aligning etch mask. Thus, vias etched between adjacent areas of metallization allow the area of the substrate allocated to the via to be significantly reduced without increasing the possibility of electrical shorts to the adjacent areas of metallization.

Mram Mtj Stack To Conductive Line Alignment Method

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US Patent:
6858441, Feb 22, 2005
Filed:
Sep 4, 2002
Appl. No.:
10/234864
Inventors:
Joachim Nuetzel - Fishkill NY,
Xian J. Ning - Mohegan Lake NY,
Gill Yong Lee - Wappingers Falls NY,
Rajiv M. Ranade - Brewster NY,
Ravikumar Ramachandran - Pleasantville NY,
Assignee:
Infineon Technologies AG - Munich
International Classification:
H01L021/28
US Classification:
438 3, 438633, 438975
Abstract:
A method of manufacturing a resistive semiconductor memory device (), comprising depositing an insulating layer () over a workpiece (), and defining a pattern for a plurality of alignment marks () and a plurality of conductive lines () within the insulating layer (). A conductive material is deposited over the wafer to fill the alignment mark () and conductive line () patterns. The insulating layer () top surface is chemically-mechanically polished to remove excess conductive material from the insulating layer () and form conductive lines (), while leaving conductive material remaining within the alignment marks (). A masking layer () is formed over the conductive lines (), and at least a portion of the conductive material is removed from within the alignment marks (). The alignment marks () are used for alignment of subsequently deposited layers of the resistive memory device ().

Cmp Process Using Indicator Areas To Determine Endpoint

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US Patent:
59727870, Oct 26, 1999
Filed:
Aug 18, 1998
Appl. No.:
9/135866
Inventors:
Karl E. Boggs - Poughkeepsie NY
Chenting Lin - Poughkeepsie NY
Joachim F. Nuetzel - Fishkill NY
Robert Ploessl - Glen Allen VA
Maria Ronay - Briarcliff Manor NY
Florian Schnabel - Wappingers Falls NY
Jeremy K. Stephens - Ossining NY
Assignee:
International Business Machines Corp. - Armonk NY
International Classification:
H01L 214763
H01L 21302
H01L 2131
US Classification:
438633
Abstract:
The method of polishing metal layers on wafers comprises the steps of: providing indicator areas on said wafer, said indicator areas having combinations of line widths and pattern factors violating existing ground rules of metal lines thereby said indicator areas being dished out during said polishing using a chemical-mechanical polisher to polish the metal layers to remove material therefrom, inspecting indicator areas on the wafer to determine an amount of material removed from said areas, and adjusting the operation of the chemical-mechanical polisher in response to the inspection of the indicator areas. The indicator areas may include macroblocks comprised of a multitude of individual blocks. The wafer may be inspected by optically identifying the polishing state of to blocks in the macroblock. Additionally, the process may be automated for mass production.

Tapered Electrode For Stacked Capacitors

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US Patent:
61658642, Dec 26, 2000
Filed:
Jul 28, 1998
Appl. No.:
9/123298
Inventors:
Hua Shen - Beacon NY
Joachim Nuetzel - Fishkill NY
Carl J. Radens - LaGrangeville NY
David Kotecki - Hopewell Junction NY
Assignee:
Siemens Aktiengesellschaft - Munich
International Classification:
H01L 2120
US Classification:
438396
Abstract:
A method for forming a stacked capacitor includes the steps of providing a first insulating layer having a conductive access path therethrough, forming a second insulating layer on the first insulating layer, forming a trench in the second insulating layer, the trench having tapered sidewalls, forming a first electrode in the trench and on the trench sidewalls, the first electrode being electrically coupled to the conductive access path, forming a dielectric layer on the first electrode and forming a second electrode on the dielectric layer. A stacked capacitor having increased surface area includes a first electrode formed in a trench provided in a dielectric material. The first electrode has tapered surfaces forming a conically shaped portion of the first electrode, the first electrode for accessing a capacitively coupled storage node.
Joachim F Nuetzel from Fishkill, NY, age ~57 Get Report