Jim Cathey Phones & Addresses
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6021 Campbell Rd, Greenacres, WA 99016 (509) 926-7801
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Liberty Lake, WA
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Spokane, WA
Publications
Wikipedia References
Jim Cathey
Work:
Jim Cathey " James J. Cathey " is a vice president of business development for Qualcomm MEMS Technologies, Inc....
Education:
Studied at:
Boise State University
Academic degree:Bachelor's Degree • Business administration
Area of science:Marketing
Skills & Activities:
Skill:
Software
Award:Excellence Award
Us Patents
Programmable Packet Processor With Flow Resolution Logic
View pageUS Patent:
7075926, Jul 11, 2006
Filed:
Dec 28, 2000
Appl. No.:
09/751194
Inventors:
Jim Cathey - Greenacres WA, US
Timothy S. Michels - Greenacres WA, US
Timothy S. Michels - Greenacres WA, US
Assignee:
Alcatel Internetworking, Inc. (PE) - Spokane WA
International Classification:
H04L 12/56
US Classification:
370389, 370392, 37039532
Abstract:
A programmable packet switching controller has a packet buffer, a pattern match module, a programmable packet classification engine and an application engine. The packet buffer stores inbound packets, and includes a header data extractor to extract header data from the inbound packets and to store the extracted header data in a header data cache. The header data extractor also generates a header data cache index and provides it to the packet classification engine for it to retrieve the extracted header data. The packet classification engine has a decision tree-based classification logic for classifying a packet. Each of the leaves of the tree represents a packet classification. The packet classification engine uses the header data cache index to retrieve the header data to perform multiple header checks, starting at a root of the tree and traversing branches until a leaf has been reached. The application engine has a number of programmable sub-engines arrayed in a pipelined architecture. The packet classification engine provides start indicators based on the packet classification to the programmable sub-engines to identify application programs to be executed.
Programmable Packet Processor With Flow Resolution Logic
View pageUS Patent:
7693149, Apr 6, 2010
Filed:
Jul 5, 2006
Appl. No.:
11/428616
Inventors:
Jim Cathey - Greenacres WA, US
Timothy S. Michels - Greenacres WA, US
Timothy S. Michels - Greenacres WA, US
Assignee:
Alcatel-Lucent USA Inc. - Murray Hill NJ
International Classification:
H04L 12/28
H04L 12/56
H04L 12/56
US Classification:
370392, 37039532, 37039552
Abstract:
A programmable packet switching controller has a packet buffer, a pattern match module, a programmable packet classification engine and an application engine. The packet buffer stores inbound packets, and includes a header data extractor to extract header data from the inbound packets and to store the extracted header data in a header data cache. The header data extractor also generates a header data cache index and provides it to the packet classification engine for it to retrieve the extracted header data. The packet classification engine has a decision tree-based classification logic for classifying a packet. Each of the leaves of the tree represents a packet classification. The packet classification engine uses the header data cache index to retrieve the header data to perform multiple header checks, starting at a root of the tree and traversing branches until a leaf has been reached. The application engine has a number of programmable sub-engines arrayed in a pipelined architecture. The packet classification engine provides start indicators based on the packet classification to the programmable sub-engines to identify application programs to be executed.
Programmable Packet Processor With Flow Resolution Logic
View pageUS Patent:
8300534, Oct 30, 2012
Filed:
Feb 16, 2010
Appl. No.:
12/706687
Inventors:
Jim Cathey - Greenacres WA, US
Timothy S. Michels - Greenacres WA, US
Timothy S. Michels - Greenacres WA, US
Assignee:
Alcatel Lucent - Paris
International Classification:
G06F 9/00
H04L 12/28
H04L 12/56
H04L 12/28
H04L 12/56
US Classification:
370235, 370392, 370394, 370412
Abstract:
A programmable packet switching controller has a packet buffer, a programmable packet classification engine and an application engine. The packet buffer stores inbound packets, and includes a header data extractor to extract header data from the inbound packets and store the extracted header data in a header data cache. The header data extractor also generates a header data cache index and provides it to the packet classification engine for it to retrieve the extracted header data. The application engine has a number of programmable sub-engines arrayed in a pipelined architecture. The packet classification engine provides start indicators based on the packet classification to the programmable sub-engines to identify application programs to be executed.
Programmable Packet Processor With Flow Resolution Logic
View pageUS Patent:
20130034101, Feb 7, 2013
Filed:
Aug 28, 2012
Appl. No.:
13/597060
Inventors:
Jim Cathey - Greenacres WA, US
Timothy S. Michels - Greenacres WA, US
Timothy S. Michels - Greenacres WA, US
International Classification:
H04L 12/56
US Classification:
370392
Abstract:
A programmable packet switching controller has a packet buffer, a pattern match module, a programmable packet classification engine and an application engine. The packet classification engine has a decision tree-based classification logic for classifying a packet. The application engine has a number of programmable sub-engines arrayed in a pipelined architecture. The sub-engines include a source lookup engine, a destination lookup engine and a disposition engine, which are used to make a disposition decision for the inbound packets in a processing pipeline.
Wikipedia
Jim Cathey
View pageJames J. Cathey is a vice president of business development for Qualcomm MEMS Technologies, Inc. (QMT), a wholly owned subsidiary of Qualcomm. Jim ...