Jerome A Duluk

20020196251, Dec 26, 2002

Aug 29, 2002

10/231436

Jerome Duluk - Palo Alto CA, US
Stephen Dodgen - Boulder Creek CA, US
Richard Hessel - Pleasanton CA, US
Emerson Fang - Fremont CA, US
Hengwei Hsu - Fremont CA, US
Jason Redgrave - Mountain View CA, US
Sushma Trivedi - Sunnyvale CA, US

Apple Computer, Inc.

G06T017/00

345/420000

Structure, apparatus, and method for performing conservative hidden surface removal in a graphics processor. Culling is divided into two steps, a magnitude comparison content addressable memory cull operation (MCCAM Cull), and a subpixel cull operation. The MCCAM Cull discards primitives that are hidden completely by previously processed geometry. The Subpixel Cull takes the remaining primitives (which are partly or entirely visible), and determines the visible fragments. In one embodiment the method of performing hidden surface removal includes: selecting a current primitive comprising a plurality of stamps; comparing stamps to stamps from previously evaluated primitives; selecting a first stamp as a currently potentially visible stamp (CPVS) based on a relationship of depth states of samples in the first stamp with depth states of samples of previously evaluated stamps; comparing the CPVS to a second stamp; discarding the second stamp when no part of the second stamp would affect a final graphics display image based on the stamps that have been evaluated; discarding the CPVS and making the second stamp the CPVS, when the second stamp hides the CPVS; dispatching the CPVS and making the second stamp the CPVS when both the second stamp and the CPVS are at least partially visible in the final graphics display image; and dispatching the second stamp and the CPVS when the visibility of the second stamp and the CPVS depends on parameters evaluated later in the computer graphics pipeline.

20030067468, Apr 10, 2003

Nov 7, 2002

10/290414

Jerome Duluk - Palo Alto CA, US
Jack Benkual - Cupertino CA, US
Shun Go - Milpitas CA, US
Sushma Trivedi - Sunnyvale CA, US
Richard Hessel - Pleasanton CA, US
Joseph Bratt - San Jose CA, US

G09G005/36

345/506000, 345/556000, 345/557000

A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A a mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.

20030179220, Sep 25, 2003

Mar 20, 2002

10/102989

Douglas Dietrich - Los Gatos CA, US
Ashutosh Rege - San Carlos CA, US
Christopher Maughan - York, GB
Jerome Duluk - Palo Alto CA, US

nVIDIA CORPORATION

G09G005/00

345/679000

A method and computer program product are provided for generating a shader program. Initially, a file associated with a graphics effect is a selected. Such file is then read and processed. A shader program is subsequently generated based on the processing of the file to apply the graphics effect to an object.

20040130552, Jul 8, 2004

Jun 9, 2003

10/458493

Jerome Duluk - Palo Alto CA, US
Richard Hessel - Pleasanton CA, US
Vaughn Arnold - Scotts Valley CA, US
Jack Benkual - Cupertino CA, US
Joseph Bratt - San Jose CA, US
George Cuan - Sunnyvale CA, US
Stephen Dodgen - Boulder Creek CA, US
Emerson Fang - Fremont CA, US
Zhaoyu Gong - Cupertino CA, US
Thomas Ho - Fremont CA, US
Hengwei Hsu - Fremont CA, US
Sidong Li - San Jose CA, US
Sam Ng - Fremont CA, US
Matthew Papakipos - Menlo Park CA, US
Jason Redgrave - Mountain View CA, US
Sushma Trivedi - Sunnyvale CA, US
Nathan Tuck - San Diego CA, US
Shun Go - Milpitas CA, US
Lindy Fung - Sunnyvale CA, US
Tuan Nguyen - San Jose CA, US
Joseph Grass - Menlo Park CA, US
Bo Hong - San Jose CA, US
Abraham Mammen - Pleasanton CA, US
Abbas Rashid - Fremont CA, US
Albert Tsay - Fremont CA, US

G06T001/20

345/506000

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

20050251787, Nov 10, 2005

Jul 13, 2005

11/181180

Douglas Dietrich - Los Gatos CA, US
Ashutosh Rege - San Carlos CA, US
Christopher Maughan - York, GB
Jerome Duluk - Palo Alto CA, US

G06F009/44

717107000, 717114000

A method and computer program product are provided for generating a shader program. Included is a file associated with a graphics effect. In use, a shader program is generated based on processing of the file to apply the graphics effect to an object.

20070165035, Jul 19, 2007

Dec 19, 2006

11/613093

Jerome Duluk - Palo Alto CA, US
Richard Hessel - Pleasanton CA, US
Vaughn Arnold - Scotts Valley CA, US
Jack Benkual - Cupertino CA, US
Joseph Bratt - San Jose CA, US
George Cuan - Sunnyvale CA, US
Stephen Dodgen - Boulder Creek CA, US
Emerson Fang - Fremont CA, US
Zhaoyu Gong - Cupertino CA, US
Thomas Ho - Fremont CA, US
Hengwei Hsu - Fremont CA, US
Sidong Li - San Jose CA, US
Sam Ng - Fremont CA, US
Matthew Papakipos - Menlo Park CA, US
Jason Redgrave - Mountain View CA, US
Sushma Trivedi - Sunnyvale CA, US
Nathan Tuck - San Diego CA, US
Shun Go - Milpitas CA, US
Lindy Fung - Sunnyvale CA, US
Tuan Nguyen - San Jose CA, US
Joseph Grass - Menlo Park CA, US
Bo Hung - San Jose CA, US
Abraham Mammen - Pleasanton CA, US
Abbas Rashid - Fremont CA, US
Albert Tsay - Fremont CA, US

Apple Computer, Inc. - Cupertino CA

G06T 1/20

345506000

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

49966669, Feb 26, 1991

Aug 12, 1988

7/231717

Jerome F. Duluk - Palo Alto CA

G11C 1300
G11C 1500

365 49

A content-addressable memory for storing a plurality of words, each word comprising a plurality of data subfields, and each data subfield comprising a plurality of data bits. Query operations simultaneously compare input data to all subfields in all words and selectably test each subfield for either equality, less-than, less-than-or-equal-to, greater-than, greater-than-or-equal-to, inequality, or don't care. A flag memory comprising a plurality of flag bits for each word stores the results of a selectable Boolean operation performed on a set of flag bits and the query results. A mask register causes selected bit positions within words to be treated as not being present. A priority resolver finds the highest priority flag bit in a particular logic state for selecting a word for reading or writing. A content-addressable memory system composed of a plurality of content-addressable memories and an external priority resolver for selecting between content-addressable memories for reading or writing.

62853783, Sep 4, 2001

Mar 8, 1999

9/264302

Jerome F. Duluk - Palo Alto CA

Apple Computer, Inc. - Cupertino CA

G06F 1500

345441

A data shifting capability that permits sorting the data in addition to searching for obtaining real-time performance in color, with high quality imagery through a simple search of a spacial database based on a rectangularly shaped search region or range search. A sorting Magnitude Comparison Content Addressable Memory (SMCCAM) performs a range search, introducing a conservative approximation of the idea Occluding Region, and provides a MCCAM wherein the data words stored in the fields are shifted to corresponding fields in an adjacent word, based on the magnitude comparisons. The 3D graphics method stores the parameters of a polygon span in a spatial database and a query operation is performed on the database to determine which of those spans, or portions of spans, are visible, and applies a rule for comparing a new span portion to an old span portion on a subspan-by-subspan basis, thereby providing additional polygon edge information within a raster line, providing anti-aliasing.