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Jerome C Bhat

from Palo Alto, CA
Age ~51
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Also known as:
Jerome Chandra Bhat, Jerome Chand Bhat, Jerome Te Bhat, Bhat Bhat
Phone and address:
4010 Ben Lomond Dr, Palo Alto, CA 94306
(415) 823-9644
Connected to:
Aarti Bhat, 28Abdul R Bhat, 62Anita W Bhat, 78Ashish Bhat, 47Balaji U Bhat, 29Bhavna Bhat, 50Chandrashekar V Bhat, 46Chandrika Bhat, 54Gireesh K Bhat, 49Jennifer L Bhat, 55

Jerome Bhat Phones & Addresses

  • 4010 Ben Lomond Dr, Palo Alto, CA 94306 (415) 823-9644
  • 1927 Hayes St, San Francisco, CA 94117
  • 470 Warren Dr, San Francisco, CA 94131 (415) 564-2753
  • San Jose, CA
  • Santa Clara, CA

Work

Company: Maxim integrated Aug 2013 Position: Opto-mechanical system architect, bio-sensors

Education

Degree: Doctorates, Doctor of Philosophy School / High School: University of Oxford 1995 to 1998 Specialities: Engineering

Skills

Product Development • Cross Functional Team Leadership • Manufacturing • Semiconductors • Design of Experiments • Product Management • R&D • Optoelectronics • Program Management • Engineering Management • Ic • Design For Manufacturing • Optics • Process Simulation • Thin Films • Testing • Electronics • Research and Development • Integration • Semiconductor Industry • Start Ups • Project Management • Solid State Lighting • Materials Science • Engineering • Characterization • Sensors • Product Design • Silicon • Simulations • Automotive • Photonics • Spc • Mems • Cmos • Embedded Systems • Failure Analysis

Languages

French

Industries

Semiconductors

Resumes

Resumes

Jerome Bhat Photo 1

Opto-Mechanical System Architect, Bio-Sensors

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Maxim Integrated
Opto-Mechanical System Architect, Bio-Sensors
Lytro Inc. Jun 1, 2012 - Jul 1, 2013
Optical Packaging Specialist
Lumileds Nov 2010 - Jun 2012
Technology Development Manager
Lumileds Feb 2007 - Nov 2010
Technical Program Manager
Lumileds Jan 2000 - Jan 2007
Led Chip Architect
Education:
University of Oxford 1995 - 1998
Doctorates, Doctor of Philosophy, Engineering University of Oxford Oct 1991 - 1995
Masters, Master of Engineering, Materials Science, Engineering
Skills:
Product Development
Cross Functional Team Leadership
Manufacturing
Semiconductors
Design of Experiments
Product Management
R&D
Optoelectronics
Program Management
Engineering Management
Ic
Design For Manufacturing
Optics
Process Simulation
Thin Films
Testing
Electronics
Research and Development
Integration
Semiconductor Industry
Start Ups
Project Management
Solid State Lighting
Materials Science
Engineering
Characterization
Sensors
Product Design
Silicon
Simulations
Automotive
Photonics
Spc
Mems
Cmos
Embedded Systems
Failure Analysis
Languages:
French

Publications

Us Patents

Monolithic Series/Parallel Led Arrays Formed On Highly Resistive Substrates

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US Patent:
6547249, Apr 15, 2003
Filed:
Mar 29, 2001
Appl. No.:
09/823824
Inventors:
Jerome Chandra Bhat - San Jose CA
Daniel Alexander Steigerwald - Cupertino CA
Assignee:
Lumileds Lighting U.S., LLC - San Jose CA
International Classification:
H01L 3300
US Classification:
277 88, 257 89, 257 90, 257 97, 257 98, 257 99
Abstract:
Series or parallel LED arrays are formed on a highly resistive substrate, such that both the p- and n-contacts for the array are on the same side of the array. The individual LEDs are electrically isolated from each other by trenches or by ion implantation. Interconnects deposited on the array connects the contacts of the individual LEDs in the array. In some embodiments, the LEDs are III-nitride devices formed on sapphire substrates. In one embodiment, two LEDs formed on a single substrate are connected in antiparallel to form a monolithic electrostatic discharge protection circuit. In one embodiment, multiple LEDs formed on a single substrate are connected in series. In one embodiment, multiple LEDs formed on a single substrate are connected in parallel. In some embodiments, a layer of phosphor covers a portion of the substrate on which one or more individual LEDs is formed.

Semiconductor Led Flip-Chip With High Reflectivity Dielectric Coating On The Mesa

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US Patent:
6630689, Oct 7, 2003
Filed:
May 9, 2001
Appl. No.:
09/852857
Inventors:
Jerome Chandra Bhat - San Francisco CA
Daniel Alexander Steigerwald - Cupertino CA
Assignee:
Lumileds Lighting, U.S. LLC - San Jose CA
International Classification:
H01L 2715
US Classification:
257 79, 257 99
Abstract:
In one embodiment of the present invention, a highly reflective dielectric stack is formed on the mesa wall of a flip-chip LED. The layers of the dielectric stack are selected to maximize reflection of light incident at angles ranging from -10 to 30 degrees, relative to the substrate. The dielectric stack is comprised of alternating low refractive index and high refractive index layers. In some embodiments, the LED is a III-nitride device with a p-contact containing silver, the dielectric stack layer adjacent to the mesa wall has a low refractive index compared to GaN, and the low refractive index layers are Al O.

Contacting Scheme For Large And Small Area Semiconductor Light Emitting Flip Chip Devices

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US Patent:
6828596, Dec 7, 2004
Filed:
Jun 13, 2002
Appl. No.:
10/172311
Inventors:
Daniel A. Steigerwald - Cupertino CA
Jerome C. Bhat - San Francisco CA
Michael J. Ludowise - San Jose CA
Assignee:
Lumileds Lighting U.S., LLC - San Jose CA
International Classification:
H01L 3300
US Classification:
257 99, 257 88, 257 93, 438 34, 438 42, 438 46, 438 47, 313505
Abstract:
In accordance with the invention, a light emitting device includes a substrate, a layer of first conductivity type overlying the substrate, a light emitting layer overlying the layer of first conductivity type, and a layer of second conductivity type overlying the light emitting layer. A plurality of vias are formed in the layer of second conductivity type, down to the layer of first conductivity type. The vias may be formed by, for example, etching, ion implantation, or selective growth of the layer of second conductivity type. A set of first contacts electrically contacts the layer of first conductivity type through the vias. A second contact electrically contacts the layer of second conductivity type. In some embodiments, the area of the second contact is at least 75% of the area of the device. In some embodiments, the vias are between 2 and 100 microns wide and spaced between 5 and 1000 microns apart.

Mount For Semiconductor Light Emitting Device

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US Patent:
6876008, Apr 5, 2005
Filed:
Jul 31, 2003
Appl. No.:
10/632719
Inventors:
Jerome C. Bhat - San Francisco CA, US
Cresente S. Elpedes - San Jose CA, US
Paul S. Martin - Pleasanton CA, US
Serge L. Rudaz - Sunnyvale CA, US
Assignee:
Lumileds Lighting U.S., LLC - San Jose CA
International Classification:
H01L029/22
H01L033/00
H01L029/207
H01L029/227
US Classification:
257 99, 257 84, 257 93, 257 98
Abstract:
A device includes a submount, and a semiconductor light emitting device mounted on first and second conductive regions on a first side of the submount in a flip chip architecture configuration. The submount has third and fourth conductive regions on a second side of the submount. The third and fourth conductive regions may be used to solder the submount to structure such as a board, without the use of wire bonds. The first and third conductive regions are electrically connected by a first conductive layer and the second and fourth conductive regions are electrically connected by a second conductive layer. The first and second conductive layers may be disposed on the outside of the submount or within the submount.

Multi-Chip Semiconductor Led Assembly

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US Patent:
6885035, Apr 26, 2005
Filed:
May 15, 2001
Appl. No.:
09/859154
Inventors:
Jerome C. Bhat - San Jose CA, US
Daniel A. Steigerwald - Cupertino CA, US
Reena Khare - Sunnyvale CA, US
Assignee:
Lumileds Lighting U.S., LLC - San Jose CA
International Classification:
H01L027/15
H01L029/20
US Classification:
257 99, 257 79, 257 81, 257 88, 257103
Abstract:
A light emitting device includes several LEDs, mounted on a shared submount, and coupled to circuitry formed on the submount. The LEDs can be of the III-Nitride type. The architecture of the LEDs can be either inverted, or non-inverted. Inverted LEDs offer improved light generation. The LEDs may emit light of the same wavelength or different wavelengths. The circuitry can couple the LEDs in a combination of series and parallel, and can be switchable between various configurations. Other circuitry can include photosensitive devices for feedback and control of the intensity of the emitted light, or an oscillator, strobing the LEDs.

Semiconductor Led Flip-Chip With Dielectric Coating On The Mesa

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US Patent:
6891197, May 10, 2005
Filed:
Jun 12, 2003
Appl. No.:
10/461173
Inventors:
Jerome C. Bhat - San Francisco CA, US
Michael J. Ludowise - San Jose CA, US
Daniel A. Steigerwald - Cupertino CA, US
Assignee:
Lumileds Lighting U.S., LLC - San Jose CA
International Classification:
H01L027/15
H01L031/12
H01L033/00
US Classification:
257 79, 257 99
Abstract:
A dielectric layer is formed on the mesa wall of a flip-chip LED. The dielectric layer is selected to maximize reflection of light incident at angles ranging from 10 degrees towards the substrate to 30 degrees away from the substrate. In some embodiments, the LED is a III-nitride device with a p-contact containing silver, the dielectric layer adjacent to the mesa wall is a material with a low refractive index compared to GaN, such as AlO.

Light Emitting Semiconductor Method And Device

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US Patent:
6946685, Sep 20, 2005
Filed:
Aug 31, 2000
Appl. No.:
09/652194
Inventors:
Daniel A. Steigerwald - Cupertino CA, US
Michael J. Ludowise - San Jose CA, US
Steven A. Maranowski - San Jose CA, US
Serge L. Rudaz - Sunnyvale CA, US
Jerome C. Bhat - San Jose CA, US
Assignee:
Lumileds Lighting U.S., LLC - San Jose CA
International Classification:
H01L029/22
US Classification:
257 94, 257 96, 257488, 257745
Abstract:
Silver electrode metallization in light emitting devices is subject to electrochemical migration in the presence of moisture and an electric field. Electrochemical migration of the silver metallization to the pn junction of the device results in an alternate shunt path across the junction, which degrades efficiency of the device. In accordance with a form of this invention, a migration barrier is provided for preventing migration of metal from at least one of the electrodes onto the surface of the semiconductor layer with which the electrode is in contact.

Integrated Reflector Cup For A Light Emitting Device Mount

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US Patent:
6995402, Feb 7, 2006
Filed:
Oct 3, 2003
Appl. No.:
10/678279
Inventors:
Michael J. Ludowise - San Jose CA, US
Jerome C. Bhat - San Francisco CA, US
Assignee:
Lumileds Lighting, U.S., LLC - San Jose CA
International Classification:
H01L 29/22
H01L 29/205
H01L 29/207
US Classification:
257 91, 257 93, 257 98, 257 99
Abstract:
A mount for a semiconductor light emitting device includes an integrated reflector cup. The reflector cup includes a wall formed on the mount and shaped and positioned to reflect side light emitted from the light emitting device along a vertical axis of the device/mount combination. The wall may be covered by a reflective material such as a reflective metal.
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Jerome C Bhat from Palo Alto, CA, age ~51 Get Report