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Jengwei Te Pan

from Scotts Valley, CA
Age ~68
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Also known as:
Jengwei T Pan, Jengwei E Pan, Jengwei Pau, Wei Pan Jengwei, I Pan
Phone and address:
114 Sherman Dr, Santa Cruz, CA 95066
Related to:
Feng PanRu C ChiuruTsang C Chen, 83Emily Chin, 35
Connected to:
Abel Pan, 61Aimee Pan, 36Bianca Pan, 55Brian W Pan, 48Chao T Pan, 49Chengzhi Pan, 47Chenxi Pan, 35Dana Pan, 39Elena Pan, 33Evan Pan, 31

Jengwei Pan Phones & Addresses

  • 114 Sherman Dr, Scotts Valley, CA 95066
  • 1532 Chaumont Dr, San Jose, CA 95118 (408) 269-7542
  • 705 Star Jasmine Ct, San Jose, CA 95131 (408) 383-9401
  • 1014 Clark Ave, Mountain View, CA 94040
  • 529 Maybell Ave, Palo Alto, CA 94306
  • Santa Clara, CA
  • 705 Star Jasmine Ct, San Jose, CA 95131 (619) 723-9329

Work

Company: Ambarella corp - Santa Clara, CA Nov 2008 Position: Member of technical staff

Education

School / High School: Arizona State University- Tempe, AZ Sep 1984 Specialities: M.S. in Electrical/Computer Engineering

Resumes

Resumes

Jengwei Pan Photo 1

Jengwei Pan San Jose, CA

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Work:
Ambarella Corp
Santa Clara, CA
Nov 2008 to Mar 2014
Member of Technical Staff
Ambarella Taiwan Ltd

2004 to 2008
Senior Director
Sun Microsystems Inc., / Afara Websystems Inc
Sunnyvale, CA
2001 to 2004
Processor and Network Product
PLX Technology Inc., / Sebring Networks
Sunnyvale, CA
1999 to 2001
CAD/Physical Design Manager
Silicon Graphics Computer Systems
Mountain View, CA
1997 to 1999
Member of Technical Staff
Exponential Technology Inc
San Jose, CA
1995 to 1997
Technical Lead/Member of Technical Staff
Silicon Graphics/MIPS Technology Inc
Mountain View, CA
1994 to 1995
Member of Technical Staff
Digital Equipment Corporation
Hudson, MA
1991 to 1994
Project Leader/Principal Software Engineer
Semiconductor Engineering Group

1987 to 1991
Senior Software Engineer
Semiconductor Engineering Group

1984 to 1987
Software Engineer II
Education:
Arizona State University
Tempe, AZ
Sep 1984
M.S. in Electrical/Computer Engineering
National Cheng Kung University
Jun 1979
B.S. in Electrical Engineering

Publications

Us Patents

Ram-Like Test Structure Superimposed Over Rows Of Macrocells With Added Differential Pass Transistors In A Cpu

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US Patent:
59517026, Sep 14, 1999
Filed:
Apr 4, 1997
Appl. No.:
8/832922
Inventors:
Hank Lim - Mountain View CA
Earl T. Cohen - Fremont CA
Peter J. Vigil - San Jose CA
Jengwei Pan - San Jose CA
James S. Blomgren - San Jose CA
Assignee:
S3 Incorporated - Santa Clara CA
International Classification:
G11C 2900
C11C 700
US Classification:
714718
Abstract:
A test structure is added to a microprocessor. The test structure is a RAM-like array of scan-clock word lines which selects a row of macrocells to be read or written. Perpendicular to the scan-clock word lines and the rows of macrocells are scan-data bit lines. Each testable macrocell has true and complement signal nodes that are connected to a pair of scan-data bit lines through a pair of n-channel pass transistors. The gates of the pass transistors are controlled by the scan-clock word line. The true and complement signal nodes are the cross-coupled inverters or gates in a latch. The latch is written or loaded by driving opposite data values onto the pair of scan-data bit lines when the pass transistors are activated by the scan-clock word line. The macrocells have random widths and thus do not form regular columns, so the columns of scan-data bit lines must be expanded to accommodate the various macrocell widths. Non-storage macrocells such as logic gates and buffers can be read but not written using the pass transistors connected to true and complement nodes in the macrocell.
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Jengwei Te Pan from Scotts Valley, CA, age ~68 Get Report