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Jeffrey C Dunnihoo

from Bertram, TX
Age ~55
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Also known as:
Jeffrey Clay Dunnihoo, Jeff Dunnihoo, Jeffrey Clay
Related to:
Edgar D Taber, 78Angela M Taber, 47Clayton O Dunnihoo, 85Elizabeth G Napolitano, 59Iris TaberElizabeth A Dunnihoo, 80Gregory A Dunnihoo, 60Taylor Taber
Connected to:
Scott K Dunnihoo, 63Rachel E Dunnill, 46Barbara C Dunnington, 78Bronwyn H Dunning, 77Bryce C Dunning, 36Caitlyn Dunning, 33Candace F Dunning, 70Charles Dunning, 78Christine E Dunning, 61Cody J Dunning, 33

Jeffrey Dunnihoo Phones & Addresses

  • Bertram, TX
  • 1113 Gemini Dr, Austin, TX 78758 (512) 339-4116
  • Arlington, TX
  • Burnet, TX
  • Liberty Hill, TX

Work

Company: Eos/esd association inc. 2008 to 2019 Position: Member

Education

School / High School: The University of Texas at Austin 1988 to 1992 Specialities: Engineering

Skills

Semiconductors • Signal Integrity • Ic • Mixed Signal • Electronics • Analog • Asic • Circuit Design • Analog Circuit Design • Soc • Pcb Design • Debugging • Simulations • Verilog • Embedded Systems • Electrical Engineering • Eda • Failure Analysis • Wireless • Product Management

Industries

Semiconductors

Resumes

Resumes

Jeffrey Dunnihoo Photo 1

Esd Systems Architect

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Eos/Esd Association Inc. 2008 - 2019
Member
Pragma Media 2008 - 2019
Publisher
Pragma Design, Inc. 2008 - 2019
Esd Systems Architect
Nxp Semiconductors Aug 2009 - Jul 2011
Esd Systems Architecture
California Micro Devices Mar 2002 - Jun 2009
Product Architect
Education:
The University of Texas at Austin 1988 - 1992
Arlington High School 1986 - 1988
Skills:
Semiconductors
Signal Integrity
Ic
Mixed Signal
Electronics
Analog
Asic
Circuit Design
Analog Circuit Design
Soc
Pcb Design
Debugging
Simulations
Verilog
Embedded Systems
Electrical Engineering
Eda
Failure Analysis
Wireless
Product Management

Publications

Us Patents

Programmable Timer Methods For Scheduling Time Slices Executed By A Controller Circuit

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US Patent:
6434708, Aug 13, 2002
Filed:
Apr 9, 1999
Appl. No.:
09/289275
Inventors:
Jeffrey C. Dunnihoo - Austin TX
Minghua Lin - Campbell CA
Assignee:
Integrated Technology Express, Inc. - Sunnyvale CA
International Classification:
G06F 104
US Classification:
713502, 713400, 713601, 709400, 710 47, 710260
Abstract:
A programmable timer is disclosed for use in conjunction with a microcontroller circuit. The timer is used as part of a time slice arbiter in a real time operating system, which arbiter manages device routines by allocating them to distinct code time slices executable by such microcontroller. The set up of time slices, including their number, sequence, duration, etc. , can be configured and optimized to achieve a desired system performance level based on characteristics of an associated system bus, devices on the bus, etc. The timer operates as a hardware controller to direct the interrupt handler to various entry points in the corresponding routines associated with interrupt based devices on a system bus.

Polarity Independent Power Supply Control Methods And Systems Using The Same

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US Patent:
6661122, Dec 9, 2003
Filed:
Dec 7, 2001
Appl. No.:
10/020142
Inventors:
Jeffrey Dunnihoo - Austin TX
Assignee:
Cirrus Logic, Inc. - Austin TX
International Classification:
H02B 124
US Classification:
307127, 307138
Abstract:
A method of controlling a power supply having an output activated in response to a first logic level of a control signal and deactivated in response to a second logic level of the control signal. A clock is generated on a second power source and used to time a time-out period of a selected number of clock periods. In response to the step of sensing, if the state of the output of the power supply is inactive through the timeout period, then the first logic level of the control signal is generated to activate the power supply for use in powering operations of an associated device. After completion of these operations, the second logic level of the control signal is generated to deactivate the power supply. If however, the state of the output of the power supply is active during the time-out period, then the first logic level of the control signal is maintained to power operations of the associated device. At the end of these operations, the second logic level of the control signal is generated to deactivate the power supply.

Bidirectional Buffer With Slew Rate Control And Method Of Bidirectionally Transmitting Signals With Slew Rate Control

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US Patent:
7321241, Jan 22, 2008
Filed:
Jun 15, 2006
Appl. No.:
11/424535
Inventors:
Chadwick N. Marak - San Jose CA, US
Jeffrey C. Dunnihoo - Bertram TX, US
Adam J. Whitworth - Los Altos CA, US
Assignee:
California Micro Devices - Milpitas CA
International Classification:
H03K 19/0175
US Classification:
326 83, 326 26
Abstract:
The present invention is directed to bidirectional buffer with slew rate control in at least one direction. The present invention is also directed to a method of bidirectionally transmitting signals with slew rate control in at least one direction.

Apparatus And Method That Provides Active Pull-Up And Logic Translation From One Signal Mode To Another Signal Mode

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US Patent:
7446565, Nov 4, 2008
Filed:
Jun 15, 2006
Appl. No.:
11/424533
Inventors:
Chadwick N. Marak - San Jose CA, US
Jeffrey C Dunnihoo - Bertram TX, US
Assignee:
California Micro Devices - Milpitas CA
International Classification:
H03K 19/094
US Classification:
326 68, 326 80, 326 81
Abstract:
Described is an integrated circuit that causes an input signal having one signal mode with a high state, a low state and a transition state to be dynamically level shifted to another signal mode with a respective high and low state, while minimizing a duration of the transition state of the output signal, wherein the one signal mode and the another signal mode have respectively different high and low state levels.

Method And Apparatus That Provides Differential Connections With Improved Esd Protection And Routing

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US Patent:
7479680, Jan 20, 2009
Filed:
Nov 30, 2005
Appl. No.:
11/291521
Inventors:
Jeffrey C Dunnihoo - Bertram TX, US
Chadwick N. Marak - San Jose CA, US
Michael S. Evans - Los Gatos CA, US
Assignee:
California Micro Devices - Milpitas CA
International Classification:
H01L 23/62
US Classification:
257355, 257546, 257666, 257691, 257692, 257697
Abstract:
The present invention provides a single ESD device package that can be used to provide ESD protection to multiple high-speed lines, in particular multiple high-speed differential lines. The present invention has various aspects. Minute parasitic matching is achieved within a single package, and TMDS signal discontinuities are reduced by allowing uniform straight through routing. Also, the straight through routing and pin locations are matched to allow those straight routing lines to mate directly to high speed lines. Also, straight ground lines having a single via are associated with the straight through routing lines.

Monolithic Multi-Channel Esd Protection Device

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US Patent:
8199447, Jun 12, 2012
Filed:
Jan 4, 2010
Appl. No.:
12/651902
Inventors:
Harry Gee - Sunnyvale CA, US
Wenjiang Zeng - Sunnyvale CA, US
Jeffrey C. Dunnihoo - Bertram TX, US
Assignee:
Semiconductor Components Industries, LLC - Phoenix AZ
International Classification:
H02H 9/00
US Classification:
361 56
Abstract:
A semiconductor device is described that includes one or more electrostatic discharge (ESD) protection circuits. Each circuit comprises reverse-biased steering diodes connected in series between power rail and signal ground, a bypass Zener diode and a substrate Zener diode. The Zener diodes provide ESD protection and the steering diode cooperate with the substrate Zener diode to provide a bypass function that is substantially symmetric about the signal ground. Noise in the circuit can be shunted using internal and/or external capacitances that can be implemented as Zener diodes.

Impedance Compensated Electrostatic Discharge Circuit For Protection Of High-Speed Interfaces And Method Of Using The Same

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US Patent:
8351170, Jan 8, 2013
Filed:
Dec 10, 2008
Appl. No.:
12/332159
Inventors:
Jeffrey C. Dunnihoo - Bertram TX, US
Richard Kimoto - Fremont CA, US
Assignee:
Semiconductor Components Industries, LLC - Phoenix AZ
International Classification:
H02H 9/00
US Classification:
361 56
Abstract:
The embodiments of the apparatus and method described herein provide an integrated ESD/EOS protection solution which simplifies system PCB design for signal integrity compliance. As part of providing this solution, it is also desired to implement improved ESD/EOS protection and improved PCB routing.

Embedded Transient Scanning System Apparatus And Methodology

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US Patent:
20130132007, May 23, 2013
Filed:
Oct 31, 2012
Appl. No.:
13/664563
Inventors:
Pragma Design, Inc. - Bertram TX, US
Jeffrey C. Dunnihoo - Bertram TX, US
Assignee:
Pragma Design, Inc. - Bertram TX
International Classification:
G01R 31/28
US Classification:
702 58, 32476203
Abstract:
Systems and methods for scanning and characterizing an integrated circuit for transient events. Embedded apparatus can detect transient events that may be incident on the integrated circuit, and moreover, identify particular nodes of the integrated circuit that are affected by the transient event. Additionally, the integrated circuit can be characterized by applying known transient pulses of varying severity to selected nodes of the integrated circuit, detecting the severity levels at which the selected nodes can fail, and storing indications pertaining to pulse severity at which selected nodes can fail. Moreover, based on the characterization, targeted protection mechanisms can be provided for nodes that are characterized as being susceptible.
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Jeffrey C Dunnihoo from Bertram, TX, age ~55 Get Report