James M Cleeves

6351406, Feb 26, 2002

Nov 15, 2000

09/714440

Mark G. Johnson - Los Altos CA
Thomas H. Lee - Cupertino CA
Vivek Subramanian - Menlo Park CA
P. Michael Farmwald - Portola Valley CA
James M. Cleeves - Redwood City CA

Matrix Semiconductor, Inc. - Santa Clara CA

G11C 1700

365103, 365164

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

6385074, May 7, 2002

Dec 22, 2000

09/748816

Mark G. Johnson - Los Altos CA
Thomas H. Lee - Cupertino CA
Vivek Subramanian - Redwood City CA
Paul Michael Farmwald - Portola Valley CA
James M. Cleeves - Redwood City CA

Matrix Semiconductor, Inc. - Santa Clara CA

G11C 1700

365103, 36523006, 365130

An integrated circuit device includes a three-dimensional memory array and array terminal circuitry for providing to selected memory cells of the array a write voltage different from a read voltage. Neither voltage is necessarily equal to a VDD power supply voltage supplied to the integrated circuit. The write voltage, particularly if greater than VDD, may be generated by an on-chip voltage generator, such as a charge pump, which may require an undesirably large amount of die area, particularly relative to a higher bit density three-dimensional memory array formed entirely in layers above a semiconductor substrate. In several preferred embodiments, the area directly beneath a memory array is advantageously utilized to layout at least some of the write voltage generator, thus locating the generator near the selected memory cells during a write operation.

6407953, Jun 18, 2002

Feb 2, 2001

09/775956

James M. Cleeves - Redwood City CA

Matrix Semiconductor, Inc. - Santa Clara CA

G11C 700

365201, 365210

In a preferred integrated circuit embodiment, a write-once memory array includes at least one test bit line which provides a respective test memory cell at the far end of each respective word line relative to its word line driver, and further includes at least one test word line which provides a respective test memory cell at the far end of each respective bit line relative to its bit line driver. An intra-layer short between word lines may be detected, such as during manufacturing testing, by biasing adjacent word lines to different voltages and detecting whether any leakage current flowing from one to another exceeds that normally accounted for by the memory cells and other known circuits. Intra-layer bit line shorts and inter-layer word line and bit line shorts may also be similarly detected. An âopenâ in a word line or bit line may be detected by trying to program the test memory cell at the far end of each such word line or bit line.

6483736, Nov 19, 2002

Aug 24, 2001

09/939431

Mark G. Johnson - Los Altos CA
Thomas H. Lee - Cupertino CA
Vivek Subramanian - Menlo Park CA
Paul Michael Farmwald - Portola Valley CA
James M. Cleeves - Redwood City CA

Matrix Semiconductor, Inc. - Santa Clara CA

G11C 1100

365130, 365164

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

6486065, Nov 26, 2002

Dec 22, 2000

09/746469

Michael A. Vyvoda - Fremont CA
N. Johan Knall - Sunnyvale CA
James M. Cleeves - Redwood City CA

Matrix Semiconductor, Inc. - Santa Clara CA

H01L 21461

438690, 438631, 438626, 438424

The present invention is a method of fabricating a semiconductor array. According to the present invention, a semiconductor layer having an upper surface is formed. A masking layer is then formed on the semiconductor layer. The masking layer is then patterned. The semiconductor layer is etched in alignment with the patterned masking layer to define memory array features. The gap between the features is filled with the dielectric material which is softer than the masking layer with respect to a planarization.

6486066, Nov 26, 2002

Feb 2, 2001

09/775761

James M. Cleeves - Redwood City CA
Michael A. Vyvoda - Fremont CA

Matrix Semiconductor, Inc. - Santa Clara CA

H01L 2182

438692, 438129, 438599, 438633, 438926

The present invention is a level of an integrated circuit. The level of integrated circuit has a first area having a plurality of features having a first density and the level of the integrated circuit has a second area adjacent to the first area wherein the second area has a plurality of dummy features having a density substantially similar to the first density.

6515904, Feb 4, 2003

Jun 29, 2001

09/895960

Christopher S. Moore - San Jose CA
Bendik Kleveland - Santa Clara CA
Roger W. March - Santa Clara CA
James M. Cleeves - Redwood City CA
Roy E. Scheuerlein - Cupertino CA

Matrix Semiconductor, Inc. - Santa Clara CA

G11C 1600

36518519, 36518522, 36518528

The preferred embodiments described herein provide a method and system for increasing programming bandwidth in a non-volatile memory device. In one preferred embodiment, a memory device is provided with a plurality of bits to be stored in a respective plurality of memory cells along a wordline. Some of the bits represent a programmed state, and others represent an un-programmed state. The duration of the programming pulse applied to the wordline is determined by the number of bits that represent the programmed state. In another preferred embodiment, the plurality of bits to be stored in the memory device comprises a first set of bits representing a modification to the stored data and a second set of bits representing an un-programmed state. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

6515923, Feb 4, 2003

Nov 15, 2001

10/002268

James M. Cleeves - Redwood City CA

Matrix Semiconductor, Inc. - Santa Clara CA

G11C 700

365201, 36518509

In a preferred integrated circuit embodiment, a write-once memory array includes at least one test bit line which provides a respective test memory cell at the far end of each respective word line relative to its word line driver, and further includes at least one test word line which provides a respective test memory cell at the far end of each respective bit line relative to its bit line driver. An intra-layer short between word lines may be detected, such as during manufacturing testing, by biasing adjacent word lines to different voltages and detecting whether any leakage current flowing from one to another exceeds that normally accounted for by the memory cells and other known circuits. Intra-layer bit line shorts and inter-layer word line and bit line shorts may also be similarly detected. An âopenâ in a word line or bit line may be detected by trying to program the test memory cell at the far end of each such word line or bit line.