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Jaime M Moreno

from Norwalk, CT
Age ~69
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Also known as:
Jaime Moreno Riano, Jaime Mokeno, Jamie Moreno
Phone and address:
2 Taylor Ave, Norwalk, CT 06854
(203) 852-1407
Related to:
Nathalia MorenoDennis ClokeGina ClokeGeorgina ClokeDavid Cloke
Connected to:
Abe P Moreno, 84Abelino Moreno, 60Adrin Moreno, 38Alana M Moreno, 34Alexia MorenoAlicia Moreno, 50Alissa Moreno, 32Allan B Moreno, 52Allem G Moreno, 53Alma A Moreno, 73

Jaime Moreno Phones & Addresses

  • 2 Taylor Ave, Norwalk, CT 06854 (203) 852-1407
  • South Norwalk, CT
  • East Haven, CT
  • Statesville, NC
  • Bridgeport, CT
  • North Canton, CT
  • Lake Forest, CA

Professional Records

Medicine Doctors

Jaime Moreno Photo 1

Jaime Moreno

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Specialties:
Family Medicine
Work:
WellmedWellmed At Crockett Park
1715 Mccullough Ave FL 2, San Antonio, TX 78212
(210) 225-5323 (phone), (210) 225-7505 (fax)
Education:
Medical School
Michigan State University College of Human Medicine
Graduated: 1984
Procedures:
Electrocardiogram (EKG or ECG)
Pulmonary Function Tests
Vaccine Administration
Conditions:
Acute Bronchitis
Bipolar Disorder
Chronic Renal Disease
Diabetes Mellitus (DM)
Disorders of Lipoid Metabolism
Languages:
English
Spanish
Description:
Dr. Moreno graduated from the Michigan State University College of Human Medicine in 1984. He works in San Antonio, TX and specializes in Family Medicine. Dr. Moreno is affiliated with Baptist Medical Center and Metropolitan Methodist Hospital.
Jaime Moreno Photo 2

Jaime Moreno

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Specialties:
Emergency Medicine
Education:
(2007)

License Records

Jaime M Moreno

Phone:
(503) 331-1650
License #:
41705 - Expired
Category:
Health Care
Issued Date:
Feb 16, 1983
Effective Date:
Feb 19, 2000
Expiration Date:
Jan 31, 1998
Type:
Medical Doctor

Business Records

Name / Title
Company / Classification
Phones & Addresses
Jaime Moreno
Managing
Triple J & L Design Build LLC
Jaime Ruedas Moreno
JAIME RUEDAS MORENO LLC
359 Gdn St 6, Hartford, CT 06112
359 Gdn St 6, Easton, CT 06612
Jaime V. Moreno
LC CONTRACTORS, LLC
Lawn/Garden Services · Nonclassifiable Establishments · Home Builders · Cabinet Refacing · Contractors · Woodworking · Ceramic Tile · Mudjacking
255 Huntington St, Shelton, CT 06484
Shelton, CT 06484
(203) 513-8526
Jaime Moreno
Principal
Solutions Cleaning & Painting
Painting/Paper Hanging Contractor
12628 Levins Hall Rd, Huntersville, NC 28078

Publications

Us Patents

Method And Apparatus For Memory Prefetching Based On Intra-Page Usage History

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US Patent:
6678795, Jan 13, 2004
Filed:
Aug 15, 2000
Appl. No.:
09/639263
Inventors:
Jaime H. Moreno - Hartsdale NY
Jude A. Rivers - Peekskill NY
John-David Wellman - Peekskill NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1208
US Classification:
711137, 711158, 711146, 711213
Abstract:
There is provided a method for fetching at least one of instructions and operand data from a second memory into a first memory of a computer system having at least one processor. The method includes the step of storing a plurality of entries in a table associated with the first memory. Each entry is associated with a memory page that includes a plurality of storage elements in the second memory, and includes information of prior access by the at least one processor to each of the plurality of storage elements. Upon a miss to the first memory from the at least one processor based upon a request, the table is searched for a given entry associated with a given page that includes a target of the request. If the given entry is found, then at least one prefetch request is generated to fetch at least one storage element included in the given page from the second memory to the first memory, based upon given information comprised in the given entry.

Method And Apparatus For Reducing Encoding Needs And Ports To Shared Resources In A Processor

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US Patent:
6704855, Mar 9, 2004
Filed:
Jun 2, 2000
Appl. No.:
09/585766
Inventors:
Erik R. Altman - Danbury CT
Jaime H. Moreno - Hartsdale NY
Mayan Moudgill - Ossining NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 930
US Classification:
712210
Abstract:
The present invention relates to a method for accessing elements from a shared resource to be used by consumers that perform actions according to corresponding operations. The method creates a packet of operations to be processed simultaneously, wherein the elements from the shared resource used by the operations are specified by source and destination identifier fields that are shared among the operations in such a way that the sum of all the elements from the shared resource used by the operations does not exceed a total number of identifiers available in the packet. The method also reads the elements from the shared resource according to the shared identifier fields specified in the packet. The method decodes a number of elements from the shared resource needed by each operation, by passing the operations to an operation decoder having a defined routing scheme based on the needs of the operations. The method also routes the elements to the consumers performing operations and resulting values to the shared resource, according to a routing signal of the operation decoder.

Method And Apparatus For History-Based Movement Of Shared-Data In Coherent Cache Memories Of A Multiprocessor System Using Push Prefetching

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US Patent:
6711651, Mar 23, 2004
Filed:
Sep 5, 2000
Appl. No.:
09/655642
Inventors:
Jaime H. Moreno - Hartsdale NY
Jude A. Rivers - Peekskill NY
John-David Wellman - Peekskill NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1300
US Classification:
711141, 711137, 711144
Abstract:
A method and apparatus are provided for moving at least one of instructions and operand data throughout a plurality of caches included in a multiprocessor computer system, wherein each of the plurality of caches is included in one of a plurality of processing nodes of the system so as to provide history-based movement of shared-data in coherent cache memories. A plurality of entries are stored in a consume after produce (CAP) table attached to each of the plurality of caches. Each of the entries is associated with a plurality of storage elements in one of the plurality of caches and includes information of prior usage of the plurality of storage elements by each of the plurality of processing nodes. Upon a miss by a processing node to a cache included therein, any storage elements that caused the miss are transferred to the cache from one of main memory and another cache. An entry is created in the table that is associated with the storage elements that caused the miss.

Method And Apparatus For Reducing Logic Activity In A Microprocessor Using Reduced Bit Width Slices That Are Enabled Or Disabled Depending On Operation Width

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US Patent:
6948051, Sep 20, 2005
Filed:
May 15, 2001
Appl. No.:
09/855241
Inventors:
Jude A. Rivers - Cortland Manor NY, US
Jaime H. Moreno - Dobbs Ferry NY, US
Vinodh R. Cuppu - Fairfax VA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F009/318
US Classification:
712200
Abstract:
A method and apparatus for reducing logic activity in a microprocessor which examines every instruction before it is executed and determines in advance the minimum appropriate datapath width (in byte or half-word quantities) necessary to accurately execute the operation. Achieving this requires two major enhancements to a traditional microprocessor pipeline. First, extra logic (potentially an extra pipeline stage for determining an operation's effective bit width—the WD width detection logic) is introduced between the Decode and Execution stages. Second, the traditional Execution stage architecture (including a register file RF and the arithmetic logical unit ALU), instead of being organized as one continuous 32-bit unit, is organized as a collection of multiple slices, where a slice can be of an 8-bit (a byte) or a 16-bit (double byte) granularity. Each slice in this case can operate independently of each other slice, and includes portion of the register file, functional unit and cache memory. Concatenating a multiple number of these slices together creates a required full width processor.

Viterbi Decoding For Simd Vector Processors With Indirect Vector Element Access

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US Patent:
6954841, Oct 11, 2005
Filed:
Sep 13, 2002
Appl. No.:
10/243567
Inventors:
Jaime Humberto Moreno - Dobbs Ferry NY, US
Fredy Daniel Neeser - Langnau am Albis, CH
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F017/16
US Classification:
712 9, 712 22, 712 32, 712222
Abstract:
A configuration of vector units, digital circuitry and associated instructions is disclosed for the parallel processing of multiple Viterbi decoder butterflies on a programmable digital signal processor (DSP) that is based on single-instruction-multiple-data (SIMD) principles and provides indirect access to vector elements. The disclosed configuration uses a processor with two vector units and associated registers, where the vector units are connected back to back for processing Viterbi decoder state metrics. Viterbi add instructions increment vectors of state metrics from a first register, performing a desired permutation of state metrics while reading them indirectly through vector pointers, and writing intermediate result vectors to a second register. Viterbi select instructions perform element-wise maximum or minimum operations on vectors from the second register to determine survivor metrics, performing a desired inverse permutation of survivor metrics while writing them back to the first register and recording the corresponding decisions in a shift register for use in a subsequent traceback operation.

Selective Bypassing Of A Multi-Port Register File

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US Patent:
7051186, May 23, 2006
Filed:
Aug 29, 2002
Appl. No.:
10/230492
Inventors:
Sameh Asaad - Briarcliff Manor NY, US
Jaime H. Moreno - Dobbs Ferry NY, US
Victor Zyuban - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 15/82
G06F 9/305
US Classification:
712 22, 712201
Abstract:
A multi-port register file may be selectively bypassed such that any element in a result vector is bypassed to the same index of an input vector of a succeeding operation when the element is requested in the succeeding operation in the same index as it was generated. Alternatively, the results to be placed in a register file may be bypassed to a succeeding operation when the N elements that dynamically compose a vector are requested as inputs to the next operation exactly in the same order as they were generated. That is, for the purposes of bypassing, the N vector elements are treated as a single entity. Similar rules apply for the write-through path.

System And Method For Instruction Memory Storage And Processing Based On Backwards Branch Control Information

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US Patent:
7130963, Oct 31, 2006
Filed:
Jul 16, 2003
Appl. No.:
10/620734
Inventors:
Sameh W. Asaad - Briarcliff Manor NY, US
Jaime H. Moreno - Dobbs Ferry NY, US
Jude A. Rivers - Cortlandt Manor NY, US
John-David Wellman - Hopewell Junction NY, US
Assignee:
International Business Machines Corp. - Armonk NY
International Classification:
G06F 12/00
US Classification:
711115, 711200
Abstract:
A system for instruction memory storage and processing in a computing device having a processor, the system is based on backwards branch control information and comprises a dynamic loop buffer (DLB) which is a tagless array of data organized as a direct-mapped structure; a DLB controller having a primary memory unit partitioned into a plurality of banks for controlling the state of the instruction memory system and accepting a program counter address as an input, the DLB controller outputs distinct signals. The system further comprises an address register located in the memory of the computing device, it is a staging register for the program counter address and an instruction fetch process that takes two cycles of the processor clock; and a bank select unit for serving as a program counter address decoder to accept the program counter address and to output a bank enable signal for selecting a bank in a primary memory unit, and a decoded address for access within the selected bank.

Cache With Selective Least Frequently Used Or Most Frequently Used Cache Line Replacement

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US Patent:
7133971, Nov 7, 2006
Filed:
Nov 21, 2003
Appl. No.:
10/719294
Inventors:
Richard Edward Matick - Cortlandt Manor NY, US
Jaime H. Moreno - Dobbs Ferry NY, US
Malcolm Scott Ware - Raleigh NC, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 12/12
US Classification:
711134, 711135, 711136, 711159
Abstract:
Methods and apparatus allowing a choice of Least Frequently Used (LFU) or Most Frequently Used (MFU) cache line replacement are disclosed. The methods and apparatus determine new state information for at least two given cache lines of a number of cache lines in a cache, the new state information based at least in part on prior state information for the at least two given cache lines. Additionally, when an access miss occurs in one of the at least two given lines, the methods and apparatus (1) select either LFU or MFU replacement criteria, and (2) replace one of the at least two given cache lines based on the new state information and the selected replacement criteria. Additionally, a cache for replacing MFU cache lines is disclosed. The cache additionally comprises MFU circuitry (1) adapted to produce new state information for the at least two given cache lines in response to an access to one of the at least two given cache lines, and (2) when a cache miss occurs in one of the at least two given cache lines, adapted to determine, based on the new state information, which of the at least two given cache lines is the most frequently used cache line.

Isbn (Books And Publications)

Los Arquitectos En Espana: Estudio Sociologico De La Profesion

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Author

Jaime Martin Moreno

ISBN #

8430906304

Universidad, Fabrica De Parados: Informe Sociologico Sobre Las Necesidades De Graduados Universitarios En Espana Y Sus Perspectivas De Empleo

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Author

Jaime Martin Moreno

ISBN #

8431617195

Franco, Franco, Franco

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Author

Jaime Martin Moreno

ISBN #

8471160056

Reformar La Universidad

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Author

Jaime Martin Moreno

ISBN #

8473640667

La Estructura Social De Las Ciudades Espanolas

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Author

Jaime Martin Moreno

ISBN #

8474760038

Sociologia De Las Profesiones En Espana

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Author

Jaime Martin Moreno

ISBN #

8474760593

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Jaime M Moreno from Norwalk, CT, age ~69 Get Report