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Isao H Nojima

from Los Altos, CA
Age ~80
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Also known as:
Isao A Nojima, Isao P Nojima
Phone and address:
475 Knoll Dr, Los Altos, CA 94024
(650) 948-2840
Related to:
Geraldo Nojima, 27Oscar M Campos, 44Patricia Hope Nojima, 71Rebecca K Nojima, 42
Connected to:
Ryuji S Nojima, 81Nima Nojoumi, 39Arsim Noka, 57John A Noke, 56William Noke, 45Tricia L Noker, 50Cameron Nokes, 33Chris Nokes, 50Craig D Nokes, 70Kyle J Nokes, 28

Isao Nojima Phones & Addresses

  • 475 Knoll Dr, Los Altos Hills, CA 94024 (650) 948-2840
  • Los Altos, CA
  • 1524 Condor Dr, Sunnyvale, CA 94087
  • Santa Clara, CA
  • 475 Knoll Dr, Los Altos, CA 94024

Work

Company: Nojima consulting Apr 1, 2005 Position: Owner

Education

Degree: Master of Science, Masters School / High School: Osaka University Apr 1967 to Mar 1969

Skills

Semiconductors

Languages

Japanese

Industries

Semiconductors

Resumes

Resumes

Isao Nojima Photo 1

Owner

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Nojima Consulting
Owner
Sst 1993 - 2005
Senior Vice President
Xicor 1980 - 1990
Design Manager
Intel Corporation Jan 19, 1977 - 1980
Senior Staff Engineer
Education:
Osaka University Apr 1967 - Mar 1969
Master of Science, Masters Tennouji High School
Osaka University, Japan 大阪大学
Skills:
Semiconductors
Languages:
Japanese

Business Records

Name / Title
Company / Classification
Phones & Addresses
Isao Nojima
Vice President
Silicon Storage Technology Inc
Semiconductors and Related Devices
1171 Sonora Ct, Sunnyvale, CA 94086
Isao Nojima
Vice President
Silicon Storage Technology Inc
Semiconductor and Related Device Manufacturing · Semiconductors & Related Devices Mfg
1171 Sonora Ct, Sunnyvale, CA 94086
(408) 735-9110, (408) 735-9036, (408) 523-7646, (408) 523-7788
Isao Nojima
Vice President
Silicon Storage Technology Inc
Semiconductors and Related Devices
1171 Sonora Ct, Sunnyvale, CA 94086

Publications

Us Patents

Differential Non-Volatile Content Addressable Memory Cell And Array

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US Patent:
6639818, Oct 28, 2003
Filed:
Mar 16, 2000
Appl. No.:
09/527373
Inventors:
Isao Nojima - Los Altos CA
Assignee:
Silicon Storage Technology, Inc. - Los Altos CA
International Classification:
G11C 1500
US Classification:
365 49
Abstract:
A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: erased in which current can flow between the first terminal and the second terminal, and programmed in which substantially no current flows between the first terminal and the second terminal. A word line connects to the control terminal of the pair of non-volatile floating gate transistors. A pair of differential data lines connects to the first terminals of each of the pair of non-volatile floating gate transistors.

Integrated Circuit With A Reprogrammable Nonvolatile Switch Having A Dynamic Threshold Voltage (Vth) For Selectively Connecting A Source For A Signal To A Circuit

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US Patent:
6809425, Oct 26, 2004
Filed:
Aug 15, 2003
Appl. No.:
10/641610
Inventors:
Bomy Chen - Cupertino CA
Isao Nojima - Los Altos CA
Hung Q. Nguyen - Fremont CA
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
H01L 27088
US Classification:
257901, 257315
Abstract:
A nonvolatile reprogrammable switch for use in a PLD or FPGA has a nonvolatile memory cell connected to the gate of an MOS transistor, which is in a well, with the terminals of the MOS transistor connected to the source of the signal and to the circuit. The nonvolatile memory cell is of a split gate type having a first region and a second region, with a channel therebetween. The cell has a floating gate positioned over a first portion of the channel, which is adjacent to the first region and a control gate positioned over a second portion of the channel, which is adjacent to the second region. The second region is connected to the gate of the MOS transistor. The cell is programmed by injecting electrons from the channel onto the floating gate by hot electron injection mechanism. The cell is erased by Fowler-Nordheim tunneling of the electrons from the floating gate to the control gate. As a result, no high voltage is ever applied to the second region during program or erase.

Unified Multilevel Cell Memory

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US Patent:
7019998, Mar 28, 2006
Filed:
Sep 9, 2003
Appl. No.:
10/659226
Inventors:
Hieu Van Tran - San Jose CA, US
Hung Q. Nguyen - Fremont CA, US
Vishal Sarin - Santa Clara CA, US
Loc B. Hoang - San Jose CA, US
Isao Nojima - Los Altos CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G11C 15/00
US Classification:
365 49, 36523003, 36518521, 711108
Abstract:
A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e. g. , CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.

Seek Window Verify Program System And Method For A Multilevel Non-Volatile Memory Integrated Circuit System

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US Patent:
7149110, Dec 12, 2006
Filed:
Dec 15, 2003
Appl. No.:
10/737689
Inventors:
Hieu Van Tran - San Jose CA, US
Hung Q. Nguyen - Fremont CA, US
Amitay Levi - Cupertino CA, US
Isao Nojima - Los Altos CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G11C 11/34
US Classification:
36518503, 36518522
Abstract:
A memory comprises a plurality of digital multilevel memory cells. A window of valid data voltages for accessing the said plurality of digital multilevel memory cells is detected. The window may be detected by incrementing a first programming voltage to program data in the plurality of memory cells and verifying whether the data in at least one of said plurality of memory cells is properly programmed. The incrementing and verifying may be repeated until data is verified to be properly programmed in one of said plurality of memory cells. The data in each memory cell of said plurality of memory cells is verified. The verification may be by incrementing a second programming voltage, and verifying whether data in each memory cell is properly programmed within a margin. The incrementing and verifying is repeated for each memory cell outside of the margin.

High-Speed And Low-Power Differential Non-Volatile Content Addressable Memory Cell And Array

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US Patent:
7196921, Mar 27, 2007
Filed:
Jul 19, 2004
Appl. No.:
10/893811
Inventors:
Vishal Sarin - Cupertino CA, US
Hieu Van Tran - San Jose CA, US
Isao Nojima - Los Altos CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G11C 15/00
US Classification:
365 49, 365202, 365227, 36518907
Abstract:
A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage.

Unified Multilevel Cell Memory

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US Patent:
7212459, May 1, 2007
Filed:
May 10, 2005
Appl. No.:
11/126495
Inventors:
Hieu Van Tran - San Jose CA, US
Hung Q. Nguyen - Fremont CA, US
Vishal Sarin - Santa Clara CA, US
Loc B. Hoang - San Jose CA, US
Isao Nojima - Los Altos CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G11C 7/02
US Classification:
365207, 365210, 36518907
Abstract:
A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e. g. , CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.

Unified Multilevel Memory Systems And Methods

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US Patent:
7336516, Feb 26, 2008
Filed:
Sep 15, 2005
Appl. No.:
11/229191
Inventors:
Hieu Van Tran - San Jose CA, US
Hung Q. Nguyen - Fremont CA, US
Vishal Sarin - Santa Clara CA, US
Loc B. Hoang - San Jose CA, US
Isao Nojima - Los Altos CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G11C 15/00
US Classification:
365 49, 36523003, 36518533
Abstract:
A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e. g. , CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.

High-Speed And Low-Power Differential Non-Volatile Content Addressable Memory Cell And Array

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US Patent:
7423895, Sep 9, 2008
Filed:
Mar 13, 2007
Appl. No.:
11/717922
Inventors:
Vishal Sarin - Cupertino CA, US
Hieu Van Tran - San Jose CA, US
Isao Nojima - Los Altos CA, US
Assignee:
Silicon Storage Technology, Inc. - Sunnyvale CA
International Classification:
G11C 15/00
US Classification:
365 491, 365202, 36518907, 36518508, 365 4911, 365 4917
Abstract:
A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage.
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Isao H Nojima from Los Altos, CA, age ~80 Get Report