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Iredamola Olusegun Olopade

from Hillsboro, OR
Age ~53
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Also known as:
Iredamola O Olopade, Iredamola O Olutola, Olopade Iredamola, A Olusegun Olopade, A Olopade, A E
Phone and address:
2627 Overlook Dr, Beaverton, OR 97124
(503) 617-6109
Related to:
Babatunde O Olutola, 51Taiwo A Olopade, 52Olopade Taiwo Olutola
Connected to:
Carlos F Olortegui, 55Judy Olortegui, 74Abayomi A Olorunfemi, 28Emmanuel O Olorunfemi, 56Rachael A Olorunisola, 57Foluke A Olorunnisola, 41Leora Olorunnisomo, 66Taiwo O Olorunniwo, 41Emanuel O Oloruntola, 39Adebisi Olorunyomi, 37

Iredamola Olopade Phones & Addresses

  • 2627 Overlook Dr, Hillsboro, OR 97124 (503) 617-6109 (503) 640-4637
  • Atlanta, GA
  • 6085 NW Sickle Ter, Portland, OR 97229 (503) 640-4637
  • Los Angeles, CA

Education

Degree: Graduate or professional degree

Resumes

Resumes

Iredamola Olopade Photo 1

Snr. Design Engineer At Intel Design

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Position:
Snr. Design Engineer at Intel Design
Location:
Portland, Oregon Area
Industry:
Design
Work:
Intel Design
Snr. Design Engineer
Education:
USC 1996 - 1997
Master of Science (MS), Computer Engineering University of Lagos 1988 - 1994
Bachelor of Science (BSc), Electrical and Electronics Engineering

Publications

Us Patents

Managing Multiple Threads In A Single Pipeline

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US Patent:
8504804, Aug 6, 2013
Filed:
Sep 13, 2012
Appl. No.:
13/613820
Inventors:
Matthew Merten - Hillsboro OR, US
Avinash Sodani - Portland OR, US
James Hadley - Portland OR, US
Alexandre Farcy - Hillsboro OR, US
Iredamola Olopade - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 15/00
G06F 9/40
G06F 9/30
US Classification:
712220, 712216
Abstract:
In one embodiment, the present invention includes a method for determining if an instruction of a first thread dispatched from a first queue associated with the first thread is stalled in a pipestage of a pipeline, and if so, dispatching an instruction of a second thread from a second queue associated with the second thread to the pipeline if the second thread is not stalled. Other embodiments are described and claimed.

Tool For Glitch Removal

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US Patent:
8555228, Oct 8, 2013
Filed:
Dec 29, 2011
Appl. No.:
13/340455
Inventors:
Nicholas Denler - Beaverton OR, US
Iredamola Dammy Olopade - Portland OR, US
Sunil Gupta - Hillsboro OR, US
Sulakshana Shyama Nath - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
716115, 716102, 716103, 716106, 716112, 716113, 716117, 716136, 716139
Abstract:
Embodiments of an electronic design automation system are generally described herein. In some embodiments, glitch-sensitive nodes in an integrated circuit design are identified. For each glitch-sensitive node, a circuit fanin cone is analyzed to look for circuit structures that can produce glitches. The integrated circuit design can be simulated and modified if the simulation indicates that a glitch would occur in the integrated circuit design.

Managing Multiple Threads In A Single Pipeline

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US Patent:
20080082796, Apr 3, 2008
Filed:
Sep 29, 2006
Appl. No.:
11/540307
Inventors:
Matthew Merten - Hillsboro OR, US
Avinash Sodani - Portland OR, US
James Hadley - Portland OR, US
Alexandre Farcy - Hillsboro OR, US
Iredamola Olopade - Hillsboro OR, US
International Classification:
G06F 9/30
US Classification:
712219
Abstract:
In one embodiment, the present invention includes a method for determining if an instruction of a first thread dispatched from a first queue associated with the first thread is stalled in a pipestage of a pipeline, and if so, dispatching an instruction of a second thread from a second queue associated with the second thread to the pipeline if the second thread is not stalled. Other embodiments are described and claimed.
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Iredamola Olusegun Olopade from Hillsboro, OR, age ~53 Get Report