Search

Ignatius S A Bezzam

from Los Altos, CA
Age ~63
Get Report
Also known as:
Ignatius S Bezzam, Bezzam S Ignatius
Phone and address:
1250 Fairway Dr, Los Altos, CA 94024
(650) 559-1956
Related to:
Eric Francis Bezzam, 30Laura M Bezzam, 61
Connected to:
Jared M Bezzant, 48Ray L Bezzant, 61Cheryl A Bezzeg, 67David J Bezzeg, 64Laura J Bezzeg, 70Heidi Bezzerides, 51Laura E Bezzi, 62Ann Bezzina, 60Rajesh Bhabu, 49Rajinder Bhachu, 39

Ignatius Bezzam Phones & Addresses

  • 1250 Fairway Dr, Los Altos, CA 94024 (650) 559-1956
  • Mountain View, CA
  • Santa Clara, CA
  • Milpitas, CA
  • 1250 Fairway Dr, Los Altos, CA 94024 (415) 425-9795

Work

Position: Food Preparation and Serving Related Occupations

Emails

i***[email protected]

Resumes

Resumes

Ignatius Bezzam Photo 1

Kendriya Vidyalaya

View page
Location:
1250 Fairway Dr, Los Altos, CA 94024
Industry:
Semiconductors
Work:
Arasan Chip Systems Inc., Dec 2008 - Sep 2010
Senior Director
Volterra 2006 - 2007
Director IC Design
Maxim Integrated Products 2001 - 2005
Senior Staff
National Semiconductor Jul 1999 - Oct 2000
Senior Design Manager
Integrated Circuit Systems (now IDT) Mar 1997 - Oct 1998
Manager
Education:
Santa Clara University 2008 - 2014
Doctor of Philosophy (Ph.D.) in progress, Electrical Engineering San Jose State University 1992 - 1993
MSEE, Semiconducor devices, process, circuits and systems Indian Institute of Technology, Madras 1978 - 1983
B.Tech, Electronics & Communication model boys high school trichur
Skills:
Semiconductors
Asic
Mixed Signal
Cmos
Ic
Analog
Soc
Integrated Circuit Design
Embedded Systems
Electronics
Vlsi
Rf
Low Power Design
Testing
Verilog
Analog Circuit Design
Fpga
Engineering Management
Silicon
Power Management
Wireless
Product Development
Hardware Architecture
Digital Signal Processors
Sensors
Simulations
Circuit Design
Coaching
Data Sheets
Matlab
R&D
Electrical Engineering
Usb
Mixed Signal Ic Design and Verification
Analog Design
Simulation
Dsp
Digital Design
Product Marketing
Interests:
Children
Languages:
English
Italian
Hindi
Malayalam
Telugu
Spanish
Sanskrit
Ignatius Bezzam Photo 2

Ignatius Bezzam

View page

Publications

Us Patents

Cmos Rail-To-Rail Input/Output Amplifier

View page
US Patent:
59297050, Jul 27, 1999
Filed:
Apr 15, 1997
Appl. No.:
8/838109
Inventors:
Michael Y. Zhang - Palo Alto CA
Ignatius Bezzam - Mountain View CA
Assignee:
Fairchild Semiconductor Corporation - South Portland MA
International Classification:
H03F 345
US Classification:
330253
Abstract:
A CMOS rail-to-rail input/output operational amplifier has constant supply current with respect to the input signal's common mode voltage. By use of current bleeders, i. e. a smaller transistor of opposite conductivity type connected in parallel with each transistor in the differential pair of transistors, there is provided constant transconductance and constant supply current for rail-to-rail operation with respect to the positive and negative supply voltages. This allows production of a low cost, high performance and small area rail-to-rail input/output operational amplifier.

Multiple Loop Radio Frequency Synthesizer

View page
US Patent:
61155861, Sep 5, 2000
Filed:
Dec 18, 1997
Appl. No.:
8/993488
Inventors:
Ignatius Bezzam - Mountain View CA
Herbe Q. H Chun - Milpitas CA
Gregory Richmond - Sunnyvale CA
Assignee:
Integrated Circuit Systems, Inc. - Valley Forge PA
International Classification:
H04B 104
US Classification:
455112
Abstract:
A radio frequency synthesizer receives a relatively low frequency input signal and synthesizes from it a high frequency output signal whose frequency can be programmed to change in fine steps, for use e. g. in cordless telephone. The frequency synthesizer includes three linked phase locked loops with a single side band mixer in one embodiment coupling two of the phase locked loops together. This provides an output signal free of in-band frequency spurs within the spacing of two channels. The synthesizer can be integrated in a single chip with a narrowband FM modulation circuit. In spite of using a novel synthesizer to achieve monolithic integration, the user programming interface and control value equations are the industry standard format.

Reduced-Power Dynamic Data Circuits With Wide-Band Energy Recovery

View page
US Patent:
20210264083, Aug 26, 2021
Filed:
May 11, 2021
Appl. No.:
17/317500
Inventors:
- Los Altos CA, US
IGNATIUS BEZZAM - LOS ALTOS CA, US
International Classification:
G06F 30/327
H03K 19/096
H03K 19/00
G06F 30/36
G06F 30/35
Abstract:
Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

Reduced-Power Electronic Circuits With Wide-Band Energy Recovery Using Non-Interfering Topologies

View page
US Patent:
20200007112, Jan 2, 2020
Filed:
Sep 12, 2019
Appl. No.:
16/569060
Inventors:
- Los Altos CA, US
Ignatius BEZZAM - Los Altos CA, US
Assignee:
REZONENT CORPORATION - Los Altos CA
International Classification:
H03K 3/012
G06F 1/06
G06F 1/10
H03K 3/356
H03K 17/687
Abstract:
Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A resonant clock distribution network comprises a plurality of resonant clock drivers that receive at least one of a plurality of reference clock signals. An energy saving component is coupled with the plurality of resonant clock drivers. The energy saving component provides for lower energy consumption by resonating with unwanted parasitic capacitance of a load capacitance. The energy saving component and the load capacitance (LC) form a series resonant frequency that is significantly greater than a clock frequency of the plurality of resonant clock drivers, so that output clock signal paths are not interfered with and so that effects on skew are minimized.

Reduced-Power Dynamic Data Circuits With Wide-Band Energy Recovery

View page
US Patent:
20190095568, Mar 28, 2019
Filed:
Jun 29, 2018
Appl. No.:
16/024613
Inventors:
- Los Altos CA, US
IGNATIUS BEZZAM - LOS ALTOS CA, US
Assignee:
REZONENT CORPORATION - LOS ALTOS CA
International Classification:
G06F 17/50
Abstract:
Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

Reduced-Power Electronic Circuits With Wide-Band Energy Recovery Using Non-Interfering Topologies

View page
US Patent:
20190097611, Mar 28, 2019
Filed:
May 8, 2018
Appl. No.:
15/974226
Inventors:
- Los Altos CA, US
IGNATIUS BEZZAM - LOS ALTOS CA, US
Assignee:
REZONENT CORPORATION - LOS ALTOS CA
International Classification:
H03K 3/012
H03K 3/356
G06F 1/10
G06F 1/06
Abstract:
Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A resonant clock distribution network comprises a plurality of resonant clock drivers that receive at least one of a plurality of reference clock signals. An energy saving component is coupled with the plurality of resonant clock drivers. The energy saving component provides for lower energy consumption by resonating with unwanted parasitic capacitance of a load capacitance. The energy saving component and the load capacitance (LC) form a series resonant frequency that is significantly greater than a clock frequency of the plurality of resonant clock drivers, so that output clock signal paths are not interfered with and so that effects on skew are minimized.

Reduced-Power Electronic Circuits With Wide-Band Energy Recovery Using Non-Interfering Topologies

View page
US Patent:
20190097626, Mar 28, 2019
Filed:
May 8, 2018
Appl. No.:
15/974240
Inventors:
- Los Altos CA, US
IGNATIUS BEZZAM - LOS ALTOS CA, US
Assignee:
REZONENT CORPORATION - LOS ALTOS CA
International Classification:
H03K 17/687
Abstract:
Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A digital logic driver comprising a pulldown switch, an energy saving component (e.g., inductor) coupled in series with the pulldown switch, and a reference supply connected in series with the energy saving component that is configured to enable the digital logic driver to resonate with a load capacitance and reuse electrical energy at the load capacitance without interfering with a signal path of the digital logic driver.
Control profile
Ignatius S A Bezzam from Los Altos, CA, age ~63 Get Report