Hugo W K Chan

6335108, Jan 1, 2002

Sep 7, 2000

09/657203

John R. LaGraff - Niskayuna NY
James M. Murduck - Redondo Beach CA
Hugo W-K. Chan - Fremont CA

TRW Inc. - Redondo Beach CA

H01L 3924

428689, 505238, 505325, 428699, 428701, 428702, 428930

An implant patterned superconductive device and a method for indirect implant-patterning of oxide superconducting materials is provided. The method forms a device having an oxide superconducting layer on a substrate, deposits a passivation layer atop the oxide superconducting layer, and implants chemical impurities in a selected portion of the superconducting layer through the passivation layer. This modifies the conductivity of the selected portion of the oxide superconducting layer and electrically isolates the selected portion from the non-selected portion of the oxide superconducting layer. The passivation layer is made of a material less susceptible to implant damage than the oxide superconducting layer to allow inhibition of the oxide superconducting layer while protecting the crystalline structure of the top surface of the oxide superconducting layer and keeping it planarized. The passivation layer is preferably a dielectric material having a crystal lattice structure which is compatible to that of the oxide superconducting layer. The method is especially efficient for the fabrication of devices with multiple layers of oxide superconductive materials because it does not degrade the epitaxial templates crystalline structure.

20030005214, Jan 2, 2003

Jul 2, 2001

09/898520

Hugo Chan - Fremont CA, US

G06F012/00

711/104000

A smart memory includes a memory array and one or more memory-intensive additional functions, all packaged in a standard memory package that has substantially the same fit and form as a standard integrated-circuit memory. One type of smart memory chip is a multi-media RAM (MMRAM) chip that provides on a single integrated-circuit chip a memory array and a compressor/decompressor (CODEC) section where connections between the memory array section and the CODEC section are on the single integrated-circuit die. The smart memory eliminates the need for additional special function integrated-circuit packages and significantly reduces the clock rate and the power consumption of a baseband chip in a personal communication device.

59125039, Jun 15, 1999

Jan 2, 1997

8/785031

Hugo W. Chan - Rancho Palos Verdes CA
Arnold H. Silver - Rancho Palos Verdes CA

TRW Inc. - Redondo Beach CA

H01L 3900
H01B 1200
B32B 1200

257663

A method of fabricating a low-inductance, in-line resistor includes the steps of: depositing a superconductive layer 12 on a base layer 14; patterning an interconnect region 16 on the superconductive layer 12; and converting the interconnect region 16 of the superconductive layer 12 to a resistor material region 18. The resistor region 18 and the superconductive layer 12 are substantially in the same plane. The method can further include the steps of depositing a conductive layer 22 on the resistor region 18 and on the photo-resist layer 20, and lifting off the photo-resist layer 20 to leave the conductive layer 22 on the resistor region 18. As such, the conductive layer 22 provides a low sheet resistivity for the resistor region 18. In another embodiment, the method includes the steps of: depositing in-situ a superconductive layer 12 on a base layer 14; depositing in-situ a conductive layer 22 on the superconductive layer 12 to form a bi-layer 24; patterning an interconnect region 16 on the bi-layer 24; and converting the interconnect region 16 of the bi-layer 24 to a resistor material region 18.

53110200, May 10, 1994

Nov 4, 1992

7/971502

Arnold H. Silver - Rancho Palos Verdes CA
Hugo W. Chan - Rancho Palos Verdes CA
Bruce J. Dalrymple - Redondo Beach CA
Szutsun S. Ou - Manhattan Beach CA
Eugene L. Dines - Lawndale CA
Susanne L. Thomasson - Redondo Beach CA

TRW Inc. - Redondo Beach CA

H01L 3922
H01L 3100

2503384

A monolithically-integrated semiconductor/ superconductor infrared detector and readout circuit providing sensitive, low-noise detection of infrared radiation for high-performance focal plane array applications. The infrared detector and readout circuit includes a semiconductor infrared detector and a semiconductor/superconductor transimpedance readout amplifier fabricated directly on the infrared detector using thin-film, integrated-circuit processing techniques. A superconducting analog-to-digital (A/D) converter digitizes the detector signals in the cryogenically cooled environment of the detector before coupling the signals to the much warmer and electromagnetically noisier environment of the back-end signal processing electronics, thus reducing noise contamination.

60666005, May 23, 2000

Jan 22, 1998

9/012090

Hugo W. Chan - Palos Verdes Estates CA

TRW Inc. - Redondo Beach CA

H01L 3924

505329

A high temperature superconductor junction and a method of forming the junction are disclosed. The junction 40 comprises a first high-T. sub. c superconductive layer (first base electrode layer) 46 on a substrate 42 and a dielectric layer 48 on the first high-T. sub. c superconductive layer. The dielectric layer and the first high-T. sub. c superconductive layer define a ramp edge 50. A trilayer SNS structure 52 is disposed on the ramp edge to form an SSNS junction. The SNS structure comprises a second high-T. sub. c superconductive layer (second base electrode layer) 54 directly on the first high-T. sub. c superconductive layer, a normal barrier layer 56 on the second high-T. sub. c superconductive layer, and a third high-T. sub. c superconductive layer 58 (counterelectrode) on the barrier layer. The ramp edge is typically formed by photoresist masking and ion-milling.

61889199, Feb 13, 2001

May 19, 1999

9/314774

John R. LaGraff - Niskayuna NY
James M. Murduck - Redondo Beach CA
Hugo W-K. Chan - Fremont CA

TRW Inc. - Redondo Beach CA

H01L 2906

505190

A SNS Josephson junction (10) is provided for use in a superconducting integrated circuit. The SNS junction (10) includes a first high temperature superconducting (HTS) layer (14) deposited and patterned on a substrate (18), such that the first HTS layer (14) is selectively removed to expose a top surface of the substrate (18) as well as to form an angular side surface (22) on the first HTS layer (14) adjacent to the exposed top surface of the substrate (18). Ion implantation is used to form a junction region (12) having non-superconducting properties along the angular side surface (22) of the first HTS layer (14). A second HTS layer (16) is then deposited and patterned over at least a portion of the first HTS layer (14) and the exposed top surface of the substrate (18), thereby forming a SNS Josephson junction.

55782264, Nov 26, 1996

Jul 18, 1995

8/503682

Hugo W. Chan - Rancho Palos Verdes CA
Arnold H. Silver - Rancho Palos Verdes CA

TRW Inc. - Redondo Beach CA

B44C 122

216 33

A multi-layer superconductive interconnect structure includes a first multi-layer substrate with a first superconducting layer (SL) deposited on a first epitaxial substrate and a first glue dielectric layer (GDL) on the first SL. A second multi-layer substrate includes a second SL deposited on a second epitaxial substrate and a second GDL on said second SL. The first GDL and the second GDL are clamped and cured together to form a composite substrate.

57803145, Jul 14, 1998

Jul 14, 1997

8/892467

Hugo Wai-Kung Chan - Rancho Palos Verdes CA

TRW Inc. - Redondo Beach CA

H01L 3924

438 2

A superconductive electrical device is operable simultaneously at relatively higher temperatures, i. e. , 60-90K, and at relatively lower temperatures, i. e. , less than 12K. The device comprises a non-superconductive substrate with two regions, a first relatively high temperature region and a second relatively low temperature region. A high temperature superconductor is on the first region and a portion of the second region. A dielectric layer is on the high temperature superconductor. A low temperature superconductor is on the second region of the substrate and on a portion of the dielectric layer. Integrated circuit chips can be secured to both superconductors, thereby yielding a superconductive multi-chip module operable at two different temperatures, such as in a cryo-cooler with two temperature stages.