Resumes
Resumes
Hugh Millis Phones & Addresses
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21746 President Point Rd, Kingston, WA 98346
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Placentia, CA
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Anaheim, CA
Publications
Us Patents
Fault Tolerant Gate Array Using Duplication Only
View pageUS Patent:
53696549, Nov 29, 1994
Filed:
Jun 23, 1992
Appl. No.:
7/902639
Inventors:
Hugh L. Millis - Placentia CA
Assignee:
Rockwell International Corporation - Seal Beach CA
International Classification:
G06F 702
H04L 100
H04L 100
US Classification:
371 681
Abstract:
The FAULT TOLERANT GATE ARRAY USING DUPLICATION ONLY shown here renders AND-drives-OR, and OR-drives-AND, gate arrays as fault tolerant as when triplicated, but does so by only duplicating the array. A test input is added to each of gates of the bottom tier of the two arrays. When a test signal is applied, the same output should be produced by both arrays. This output should be the same as an expected test output, which is known in advance. When the test signal is withdrawn, the two arrays should continue to produce the same output as each other, although it may or may not be the same as the output under test. If any of these three conditions is not met, the failure may be used to determine the correct output, the failed array, and the nature of the failure.