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Hsingjen C Wann

from Carmel, NY
Age ~58
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Also known as:
Hsingjen Jen Wann, Hsingjen J Wann, Hsing Jen Wann, Hsing J Wann, Jen C Wann, Clement Wann, N Jen G, N Wann, Jen Wann Hsing, Jen Wann Hsingjen
Phone and address:
1179 Barrett Cir, Kent Lakes, NY 10512
(845) 225-4785
Related to:
Mary Taifang Wang, 47Vivian Wang, 38Xi C JillyYuh H ChunNorman Chan, 53
Connected to:
Amanda D Wann, 39Geoffrey J Wann, 31Glenda W Wann, 79Lansia L Wann, 41Melody J Wann, 62Susan G Wann, 73Terry D Wann, 61George Wanna, 52Carissa A Wannall, 41Corey J Wannamaker, 35

Hsingjen Wann Phones & Addresses

  • 1179 Barrett Cir, Carmel, NY 10512 (845) 225-4785
  • Kent Lakes, NY
  • Fishkill, NY
  • Briarcliff Manor, NY
  • San Jose, CA
  • Roswell, GA
  • Albany, CA
  • Wappingers Falls, NY
  • Mohegan Lake, NY
  • Belmont, CA

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Publications

Us Patents

Dense Sram Cells With Selective Soi

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US Patent:
6876040, Apr 5, 2005
Filed:
Dec 12, 2003
Appl. No.:
10/735169
Inventors:
Hsingjen Wann - Carmel NY, US
Ying Zhang - Yorktown Heights NY, US
Robert C. Wong - Poughkeepsie NY, US
An Steegen - Stamford CT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L027/01
H01L027/12
H01L031/0392
H01L029/76
H01L029/94
US Classification:
257351, 257369, 257903
Abstract:
A SRAM cell fabricated in SSOI (selective silicon on insulator) comprises cross coupled PFET pull-up devices P, Pand NFET pull-down devices N, N, with the P, Pdevices being connected to the power supply and the N, Ndevices being connected to the ground. A first passgate NL is coupled between a first bitline and the junction of the devices Pand N, with its gate coupled to a wordline, and a second passgate NR is coupled between a second bitline and the junction of devices Pand N, with its gate coupled to the wordline. Each of the pull-up devices P, P, the pull-down devices N, N, and the first and second passgates NL, NR are fabricated with selective SOI, with buried oxide being selectively provided under the drains of the pull-up devices Pand P, the drains of the pull-down devices Nand N, and the sources and drains of the passgate devices NL and NR.

Formation Of Improved Soi Substrates Using Bulk Semiconductor Wafers

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US Patent:
7452784, Nov 18, 2008
Filed:
May 25, 2006
Appl. No.:
11/420279
Inventors:
William K. Henson - Peekskill NY, US
Dureseti Chidambarrao - Weston CT, US
Kern Rim - Yorktown Heights NY, US
Hsingjen Wann - Kent Lakes NY, US
Hung Y. Ng - New Milford NJ, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/76
US Classification:
438421, 438455, 257E21545
Abstract:
The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.

Formation Of Improved Soi Substrates Using Bulk Semiconductor Wafers

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US Patent:
7932158, Apr 26, 2011
Filed:
Oct 20, 2008
Appl. No.:
12/254197
Inventors:
William K. Henson - Peekskill NY, US
Dureseti Chidambarrao - Weston CT, US
Kern Rim - Yorktown Heights NY, US
Hsingjen Wann - Kent Lakes NY, US
Hung Y. Ng - New Milford NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/76
US Classification:
438422, 438400, 438404
Abstract:
The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.

Formation Of Improved Soi Substrates Using Bulk Semiconductor Wafers

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US Patent:
8268698, Sep 18, 2012
Filed:
Mar 1, 2011
Appl. No.:
13/037608
Inventors:
William K. Henson - Peekskill NY, US
Dureseti Chidambarrao - Weston CT, US
Kern Rim - Yorktown Heights NY, US
Hsingjen Wann - Kent Lakes NY, US
Hung Y. Ng - New Milford NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/76
US Classification:
438421
Abstract:
The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.

Structure And Method For High Performance Interconnect

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US Patent:
20130015581, Jan 17, 2013
Filed:
Jul 13, 2011
Appl. No.:
13/182368
Inventors:
Hsingjen Wann - Carmel NY, US
Ting-Chu Ko - Hsinchu, TW
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. - Hsin-Chu
International Classification:
H01L 23/48
H01L 21/768
US Classification:
257751, 438653, 257E23011, 257E21584
Abstract:
The present disclosure provides an integrated circuit structure. The integrated circuit structure includes a substrate having an IC device formed therein; a first dielectric material layer disposed on the substrate and having a first trench formed therein; and a first composite interconnect feature disposed in the first trench and electrically coupled with the IC device. The first composite interconnect feature includes a first barrier layer disposed on sidewalls of the first trench; a first metal layer disposed on the first barrier layer; and a first graphene layer disposed on the metal layer.

System And Method For Hierarchy Reconstruction From Flattened Graphic Database System Layout

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US Patent:
20130019219, Jan 17, 2013
Filed:
Jul 13, 2011
Appl. No.:
13/182338
Inventors:
Shu-Yu Chen - Hsinchu City, TW
Yi-Tang Lin - Hsinchu City, TW
Cheok-Kei Lei - Andar, MO
Hsiao-Hui Chen - Hsinchu City, TW
Yu-Ning Chang - Hsinchu City, TW
Hsingjen Wann - Carmel NY, US
Chih-Sheng Chang - Hsinchu, TW
Chien-Wen Chen - Hsinchu City, TW
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. - Hsin-Chu
International Classification:
G06F 17/50
US Classification:
716111
Abstract:
System and method for hierarchy reconstruction from a flattened layout are described. In one embodiment, a method for producing a reconstructed layout for an integrated circuit design from an original layout and a revised layout includes, for each pattern of the original layout, determining a pattern of the revised layout that corresponds to the pattern of the original layout; and assigning the corresponding pattern of the revised layout to a temporary instance, the temporary instance corresponding to an instance of the pattern of the original layout and citing to a temporary cell. The method further includes creating a temporary reconstructed layout from the temporary instances; and producing the reconstructed layout from the temporary reconstructed layout, wherein a hierarchy of the reconstructed layout is similar to a hierarchy of the original layout.

(110) Surface Orientation For Reducing Fermi-Level-Pinning Between High-K Dielectric And Group Iii-V Compound Semiconductor Substrate

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US Patent:
20130126985, May 23, 2013
Filed:
Nov 18, 2011
Appl. No.:
13/299529
Inventors:
Chao-Ching Cheng - Hsinchu City, TW
Chih-Hsin Ko - Fongshan City, TW
Hsingjen Wann - Carmel NY, US
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. - Hsin-Chu
International Classification:
H01L 29/772
H01L 21/28
US Classification:
257411, 438590, 257E29242, 257E2119
Abstract:
A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.

Methods For Making High-Aspect Ratio Holes In Semiconductor And Its Application To A Gate Damascene Process For Sub- 0.05 Micron Mosfets

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US Patent:
60636998, May 16, 2000
Filed:
Aug 19, 1998
Appl. No.:
9/136325
Inventors:
Hussein Ibrahim Hanafi - Basking Ridge NJ
Young Hoon Lee - Somers NY
Hsingjen Wann - Briarcliff Manor NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 213205
H01L 214763
US Classification:
438589
Abstract:
The present invention provides a process of fabricating high aspect ratio holes (H/L is 2 or greater) in a semiconductor structure wherein a masked gate-like reactive ion etch process is employed. The high aspect ratio holes have perfectly vertical sidewalls thus they are particularly useful in fabricating gate electrodes of sub-0. 05. mu. m MOSFETs using a damascene process.
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Hsingjen C Wann from Carmel, NY, age ~58 Get Report