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Hock Chuen So

from Saratoga, CA
Age ~67
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Also known as:
Hock C So, Hock Christine So, Hock Cheun So, Chuen So Hock, Hock Cso, So Hock, So Hc
Phone and address:
14001 Alta Vista Ave, Saratoga, CA 95070
(408) 872-0862
Related to:
Natalie So, 30Christine L Siu, 62
Connected to:
Adrienne M So, 41Alan So, 43Albert L So, 52Angie O So, 61Ann C So, 67Bob W So, 46Charissa H So, 47Edison So, 42Erica W So, 43Eunice J So, 48

Hock So Phones & Addresses

  • 14001 Alta Vista Ave, Saratoga, CA 95070 (408) 872-0862
  • 3722 Farm Hill Blvd, Redwood City, CA 94061
  • 230 Biarritz Ct, Redwood City, CA 94065
  • Walnut, CA
  • Santa Clara, CA
  • Milpitas, CA

Resumes

Resumes

Hock So Photo 1

Principal Engineer At Sandisk Corporation

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Location:
Berkeley, CA
Industry:
Semiconductors
Work:
Sandisk
Principal Engineer at Sandisk Corporation
Education:
University of California, Berkeley 1979 - 1980
Masters, Master of Science In Electrical Engineering Caltech 1975 - 1979
Bachelors, Bachelor of Science, Engineering
Skills:
Semiconductors
Asic
Soc
Cmos
Mixed Signal
Debugging
Ic
Vlsi
Engineering Management
Flash Memory
Semiconductor Industry
Embedded Systems
Integrated Circuit Design
Hock So Photo 2

Hock So

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Hock So Photo 3

Principal Engineer At Sandisk

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Position:
Principal Engineer at SanDisk
Location:
San Francisco Bay Area
Industry:
Semiconductors
Work:
SanDisk
Principal Engineer

Publications

Us Patents

Flash Memory Permitting Simultaneous Read/Write And Erase Operations In A Single Memory Array

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US Patent:
6345000, Feb 5, 2002
Filed:
Nov 25, 1998
Appl. No.:
09/199971
Inventors:
Sau C. Wong - Hillsborough CA
Hock C. So - Redwood City CA
Cheng-Yuan Michael Wang - San Jose CA
Roger Ying Kuen Lo - San Jose CA
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
G11C 1604
US Classification:
36518529, 36518505, 36518511
Abstract:
A non-volatile Flash memory simultaneously performs an erase operation and a write or read operation in the same array of memory cells. The memory has a row based sector architecture, i. e. , sectors that contain one or more complete rows of memory cells. During an erase operation, an erase voltage applied to the source lines for one or more rows corresponding to a sector does not affect write or read operations being performed in other sectors, i. e. , other rows. Similarly, voltages applied to row lines for access to a memory cell have no effect on the erase operation being performed in another sector. A column line voltage applied for access to a memory cell has little affect on the erase operation. The memory can implement a look-ahead erase for a continuous reading or writing operation.

Charge Pump Circuit Adjustable In Response To An External Voltage Source

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US Patent:
6370075, Apr 9, 2002
Filed:
Jun 29, 1999
Appl. No.:
09/343206
Inventors:
Andreas M. Haeberli - Campbell CA
Sau C. Wong - Hillsborough CA
Hock C. So - Redwood City CA
Carl W. Werner - San Jose CA
Cheng-Yuan Michael Wang - San Jose CA
Leon Sea Jiunn Wong - Sunnyvale CA
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
G11C 700
US Classification:
365226, 36518909, 36518907, 327536
Abstract:
An integrated circuit detects the voltage level of the supply voltage to the integrated circuit. Circuity on the integrated circuit including the charge pump circuity adjusts to operate more effectively or efficiently at the voltage level of the supply voltage.

Data Management For Multi-Bit-Per-Cell Memories

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US Patent:
6532556, Mar 11, 2003
Filed:
Jan 27, 2000
Appl. No.:
09/492949
Inventors:
Sau Ching Wong - Hillsborough CA
Hock Chuen So - Redwood City CA
Assignee:
Multi Level Memory Technology - San Jose CA
International Classification:
G11C 2900
US Classification:
714702, 714718, 711220
Abstract:
A multi-bit-per-cell memory reduces the effect of defects and data errors by scrambling data bits before writing data. The scrambling prevents storage of consecutive bits in the same memory cell. When a memory cell is defective or produces an error, the bits read from the memory cell do not create consecutive bit errors that would be noticeable or uncorrectable. An error or a defect in a multi-bit memory cell causes at most scattered bit errors. Scramblers in multi-bit-per-cell memories can include 1) hardwired lines crossing between an input port and an output port, 2) programmable wiring options, 3) a linear buffer where reads from the buffer use addresses with swapped bits, or 4) a buffer array that switches between incrementing a row address first and incrementing a column address first when accessing memory cells in the buffer array.

Integrated Circuit With Analog Or Multilevel Storage Cells And User-Selectable Sampling Frequency

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US Patent:
6549456, Apr 15, 2003
Filed:
Jun 29, 1999
Appl. No.:
09/343117
Inventors:
Carl W. Werner - San Jose CA
Andreas M. Haeberli - Campbell CA
Leon Sea Jiunn Wong - Sunnyvale CA
Cheng-Yuan Michael Wang - San Jose CA
Hock C. So - Redwood City CA
Sau C. Wong - Hillsborough CA
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
G11C 1604
US Classification:
36518503, 365233
Abstract:
Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells ( ) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The users selection of the sampling frequency is stored within the integrated circuit.

Adjustable Circuits For Analog Or Multi-Level Memory

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US Patent:
6556465, Apr 29, 2003
Filed:
Mar 27, 2002
Appl. No.:
10/109353
Inventors:
Andreas M. Haeberli - Campbell CA
Sau C. Wong - Hillsborough CA
Hock C. So - Redwood City CA
Carl W. Werner - San Jose CA
Cheng-Yuan Michael Wang - San Jose CA
Leon Sea Jiunn Wong - Sunnyvale CA
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
G11C 2700
US Classification:
365 45, 36518909, 365226
Abstract:
An integrated circuit detects the voltage level of the supply voltage to the integrated circuit. Circuity on the integrated circuit including the charge pump circuity adjusts to operate more effectively or efficiently at the voltage level of the supply voltage.

Charge Pump Circuit Adjustable In Response To An External Voltage Source

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US Patent:
6760262, Jul 6, 2004
Filed:
Mar 4, 2003
Appl. No.:
10/382333
Inventors:
Andreas M. Haeberli - Campbell CA
Sau C. Wong - Hillsborough CA
Hock C. So - Redwood City CA
Carl W. Werner - San Jose CA
Cheng-Yuan Michael Wang - San Jose CA
Leon Sea Jiunn Wong - Sunnyvale CA
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
G11C 700
US Classification:
36518909, 36518907, 365226, 327536
Abstract:
An integrated circuit detects the voltage level of the supply voltage to the integrated circuit. Circuity on the integrated circuit including the charge pump circuity adjusts to operate more effectively or efficiently at the voltage level of the supply voltage.

Multi-Bit-Per-Cell Flash Eeprom Memory With Refresh

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US Patent:
6898117, May 24, 2005
Filed:
Oct 18, 2001
Appl. No.:
10/045505
Inventors:
Hock C. So - Redwood City CA, US
Sau C. Wong - Hillsborough CA, US
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
G11C016/04
US Classification:
36518503, 36518524, 36518525
Abstract:
A memory architecture for a non-volatile analog or multiple-bits-per-cell memory includes multiple separate memory arrays and multiple read/write pipelines. The multiple read/write pipelines share a read circuit and/or a write circuit to reduce the circuit area of each pipeline and the circuit area of the memory as a whole. In one embodiment, a shared write circuit generates a programming voltage that changes with an input signal representing values to be written to the memory. Each pipeline includes a sample-and-hold circuit that samples the programming voltage when the pipeline begins a write operation. The write circuit can additionally generate a verify voltage that a second sample-and-hold circuit in each pipeline samples when starting a write operation.

Integrated Circuit With Analog Or Multilevel Storage Cells And User-Selectable Sampling Frequency

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US Patent:
7106632, Sep 12, 2006
Filed:
Feb 5, 2003
Appl. No.:
10/359476
Inventors:
Carl W. Werner - San Jose CA, US
Andreas M. Haeberli - Campbell CA, US
Leon Sea Jiunn Wong - Sunnyvale CA, US
Cheng-Yuan Michael Wang - San Jose CA, US
Hock C. So - Redwood City CA, US
Sau C. Wong - Hillsborough CA, US
Assignee:
SanDisk Corporation - Milpitas CA
International Classification:
G11C 7/10
US Classification:
36518902, 36518907
Abstract:
Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells () capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.
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Hock Chuen So from Saratoga, CA, age ~67 Get Report