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Hermann Wienchol

from Sugar Land, TX
Age ~55
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Also known as:
Wienchol Hermann, Herman Wienchol, Hermann L
Connected to:
Jeffrey J Wienckowski, 46Justin Wienckowski, 44Thomas Wienckowski, 65Erik J Wienclawski, 43John Wienclaw, 95Noni Wiencrot, 76Jan G Wienczkowski, 67Michael T Wienczkowski, 41Wayne J Wienecke, 55Albert R Wieneke, 92

Hermann Wienchol Phones & Addresses

  • Sugar Land, TX
  • Cary, NC
  • 5711 White Clover Dr, Richmond, TX 77469
  • Stafford, TX
  • 412 Fincastle Dr, Raleigh, NC 27607 (919) 851-5179
  • Santa Clara, CA
  • Santa Cruz, CA
  • San Jose, CA

Work

Company: Nanya technology delaware Jan 2008 Position: Staff engineer, dram development

Education

School / High School: Fachhochschule Muenchen- Mnchen Feb 1997 Specialities: Diplom in electrical engineering

Skills

Operating Systems: Win [] Debian/Suse Li... • Mac OS X • Unix • Solaris • VMS Programming Languages: C • Turbo Pascal • Visual Basic • C++ • Matlab • HTML Documentation: MS Office • Adobe Framemaker * Project Planning: MS ... • VHDL * CAD Tools: - characterization: Ma... • ChaMoTo - layout: Assura • Hercules - simulation: NCverilog • Verilog-XL • Verifault-XL • VHDL • Nanosim • Finesim • HSpice • Titan * Other: Adobe Photoshop • Illustrator • Acrobat • Flash

Languages

English • German • Spanish

Industries

Information Technology And Services

Resumes

Resumes

Hermann Wienchol Photo 1

Director

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Location:
1321 east Cooper Dr, Palatine, IL 60074
Industry:
Information Technology And Services
Work:
Nanya Technology
Design Engineering Manager
Hewlett-Packard Nov 2015 - Jul 2018
Memory Technologist
Hp Nov 2012 - Nov 2015
Memory Technologist
Nanya Technology Jan 2008 - Sep 2012
Staff Design Engineer and Project Lead
Atr International Oct 2007 - Dec 2007
Technical Consultant
Education:
Munich University of Applied Sciences 1990 - 1996
Masters, Electronics Engineering, Electronics
Skills:
Ic
Cmos
Asic
Semiconductors
Vlsi
Cadence Virtuoso
Logic Design
Verilog
Dram
Physical Design
Analog
Circuit Design
Debugging
Mixed Signal
Integrated Circuit Design
Simulations
Application Specific Integrated Circuits
Languages:
English
German
Spanish
Hermann Wienchol Photo 2

Hermann Wienchol Richmond, TX

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Work:
NANYA Technology Delaware

Jan 2008 to 2000
STAFF ENGINEER, DRAM development
ATR International
San Jose, CA
Oct 2007 to Dec 2007
CONTRACTOR
QIMONDA North America
Cary, NC
Jul 2006 to Oct 2007
STAFF ENGINEER, DRAM development
INFINEON Technologies North America
Cary, NC
Apr 2003 to Jun 2006
SENIOR ENGINEER, DRAM development
INFINEON Technologies North America
Santa Cruz, CA
Jul 2000 to Mar 2003
STAFF ENGINEER
INFINEON Technologies North America
San Jose, CA
Apr 1999 to Jul 2000
SENIOR ENGINEER
SIEMENS AG
Mnchen
Feb 1997 to Mar 1999
ENGINEER, library development
Education:
Fachhochschule Muenchen
Mnchen
Feb 1997
Diplom in electrical engineering
CMOS fabrication Center Munich
Mnchen
Sep 1995 to Sep 1995
o Technical University Munich
Mnchen
Feb 1995 to May 1995
mechanical engineering
o Technical University Munich
Mnchen
Mar 1994 to Aug 1994
mechanical engineering
Skills:
Operating Systems: Win [] Debian/Suse Linux, Mac OS X, Unix, Solaris, VMS Programming Languages: C, Turbo Pascal, Visual Basic, C++, Matlab, HTML Documentation: MS Office, Adobe Framemaker * Project Planning: MS Project * Hardware Description Languages: Verilog, VHDL * CAD Tools: - characterization: MasterToolbox, ChaMoTo - layout: Assura, Hercules - simulation: NCverilog, Verilog-XL, Verifault-XL, VHDL, Nanosim, Finesim, HSpice, Titan * Other: Adobe Photoshop, Illustrator, Acrobat, Flash,

Publications

Us Patents

Fuse Sensing Method And Apparatus

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US Patent:
20080265907, Oct 30, 2008
Filed:
Apr 27, 2007
Appl. No.:
11/741351
Inventors:
Hermann Wienchol - Raleigh NC, US
International Classification:
H01H 85/30
US Classification:
324550
Abstract:
Fuse sensing is performed in an integrated circuit by selecting a reference voltage based on a temperature measurement acquired by the integrated circuit. A state of one or more fuses included in the integrated circuit is sensed based on the reference voltage during normal operation of the integrated circuit. The state of the one or more fuses may be sensed during testing of the integrated circuit based on a different reference voltage.

Memory Redundancy Method And Apparatus

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US Patent:
20080270828, Oct 30, 2008
Filed:
Apr 27, 2007
Appl. No.:
11/741337
Inventors:
Hermann Wienchol - Raleigh NC, US
International Classification:
G01R 31/28
US Classification:
714 12
Abstract:
Redundancy is provided in a memory device having a configurable data bus organization by associating a redundant memory location with a defective memory location and configuring a size of the redundant memory location based on the current data bus organization of the memory device.

Test Mode Initialization Device And Method

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US Patent:
20130021863, Jan 24, 2013
Filed:
Jul 22, 2011
Appl. No.:
13/188463
Inventors:
Hermann Wienchol - Richmond TX, US
International Classification:
G11C 29/14
US Classification:
365201
Abstract:
A die includes: a plurality of efuses, for respectively generating a plurality of test-mode signals; a control unit, coupled to a first control signal, for generating a plurality of control bits; a multiplexer, coupled to the plurality of test-mode signals and the control unit, for muxing the plurality of test-mode signals in series in response to the plurality of control bits; at least an address block, for receiving a specific test-mode signal; and at least a local test-mode block coupled to the address block. The local test-mode block comprises: a latch, for latching a specific test-mode signal and releasing the latched test-mode signal to the address block in response to a second control signal; a first decoder, for releasing the specific test-mode signal to the latch in response to the plurality of control bits; and a second decoder, for generating the second control signal to the latch.

Modular Server Design

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US Patent:
20200093021, Mar 19, 2020
Filed:
Sep 14, 2018
Appl. No.:
16/131441
Inventors:
- Houston TX, US
David W. Engler - Cypress TX, US
Hermann Wienchol - Houston TX, US
International Classification:
H05K 7/14
G02B 6/42
Abstract:
A modular compute platform including an enclosure, a first module including an application specific integrated circuit, the first module being disposed in the enclosure, a second module including an input/output device, the second module being disposed in the enclosure, the input/output device connected to the first module through a first cable, and a third module including a media device disposed in the enclosure, the media device connected to the first module through a second cable.

Modular Server Architectures

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US Patent:
20190373754, Dec 5, 2019
Filed:
Jun 5, 2018
Appl. No.:
16/000791
Inventors:
- Houston TX, US
Hermann Wienchol - Houston TX, US
David Engler - Cypress TX, US
International Classification:
H05K 7/14
Abstract:
Examples relate to a modular server architecture that comprises a server chassis, a plurality of independent resource modules releasable attached to the server chassis a memory semantic protocol controller connected to the plurality of independent resource modules. Each one of the resource modules of the plurality of resource modules has a distinct Printed Circuit Board (PCB). The memory semantic media controller is to manage the plurality of independent resource modules.
Control profile
Hermann Wienchol from Sugar Land, TX, age ~55 Get Report