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Harrick M Vin

from Austin, TX
Age ~58

Harrick Vin Phones & Addresses

  • 11223 Cedarcliffe Dr, Austin, TX 78750 (512) 918-9729
  • Hillsboro, OR
  • San Diego, CA
  • Brooklyn, NY
  • La Jolla, CA
  • 11223 Cedarcliffe Dr, Austin, TX 78750 (512) 658-0790

Work

Position: Executive, Administrative, and Managerial Occupations

Emails

Publications

Isbn (Books And Publications)

Multimedia Computing and Networking 1996: 29-31 January 1996, San Jose, California

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Author

Harrick M. Vin

ISBN #

0819420417

Multimedia Computing and Networking 1997: 10-11 February, 1997, San Jose, California

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Author

Harrick M. Vin

ISBN #

0819424315

Us Patents

Apparatus And Method For Two-Stage Packet Classification Using Most Specific Filter Matching And Transport Level Sharing

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US Patent:
7525958, Apr 28, 2009
Filed:
Apr 8, 2004
Appl. No.:
10/822034
Inventors:
Alok Kumar - Santa Clara CA, US
Michael E. Kounavis - Hillsboro OR, US
Raj Yavatkar - Portland OR, US
Prashant R Chandra - Sunnyvale CA, US
Sridhar Lakshmanamurthy - Sunnyvale CA, US
Chen-Chi Kuo - Pleasanton CA, US
Harrick M. Vin - Austin TX, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H04L 12/56
H04L 12/28
US Classification:
370386, 370392, 3703953, 370389, 370413, 370356
Abstract:
A method and apparatus for two-stage packet classification. In the first stage, which may be implemented in software, a packet is classified on the basis of the packet's network path and, perhaps, its protocol. In the second stage, which may be implemented in hardware, the packet is classified on the basis of one or more transport level fields of the packet. An apparatus of two-stage packet classification may include a processing system for first stage code execution, a classification circuit for performing the second stage of classification, and a memory to store a number of bins, each bin including one or more rules.

Method And System For Configuring Network Processing Software To Exploit Packet Flow Data Locality

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US Patent:
7536674, May 19, 2009
Filed:
Aug 13, 2003
Appl. No.:
10/639501
Inventors:
James L. Jason - Hillsboro OR, US
Aaron R. Kunze - Portland OR, US
Erik J. Johnson - Portland OR, US
Harrick Vin - Austin TX, US
Ravi Sahita - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/44
G06F 9/445
US Classification:
717106, 717172, 717177
Abstract:
Embodiments of the present invention relate to a method and system for automatically configuring network processing software to reduce memory latency associated with parallel processing using a plurality of processing elements.

Merger Of Tables Storing Protocol Data Unit Related Data

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US Patent:
7725886, May 25, 2010
Filed:
Apr 1, 2003
Appl. No.:
10/405787
Inventors:
Aaron R. Kunze - Portland OR, US
Erik J. Johnson - Portland OR, US
James L. Jason - Hillsboro OR, US
Harrick M. Vin - Austin TX, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/45
US Classification:
717159
Abstract:
In general, in one aspect, the disclosure describes a method of determining if a first query for data related to a protocol data unit in a first table is a query to a table merged into a combination table formed from multiple tables. If so, the method can generate a second query for the first query for data stored by the combination table.

Run-Time Personalization Architecture

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US Patent:
20010054176, Dec 20, 2001
Filed:
Feb 8, 2001
Appl. No.:
09/780945
Inventors:
Harrick Vin - Austin TX, US
Syed Husain - Austin TX, US
International Classification:
G06F009/45
US Classification:
717/005000
Abstract:
Computer executable logic is provided which comprises logic that extracts information and/or application front ends from a network or local resource; logic that manipulates and/or enhances extracted content to new looks and feels or with modified functionality; and logic that provides a mechanism by which complex transformations and applications can be constructed by composing any number of manipulation and extraction operations at run-time.

Assigning A Process To A Processor For Execution

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US Patent:
20050039184, Feb 17, 2005
Filed:
Aug 13, 2003
Appl. No.:
10/640879
Inventors:
Aaron Kunze - Portland OR, US
Jayaram Mudigonda - Austin TX, US
Harrick Vin - Austin TX, US
Arun Raghunath - Beaverton OR, US
International Classification:
G06F009/46
US Classification:
718103000
Abstract:
A method for assigning a process to a processor for execution includes determining a value that represents a degree of information sharing between one process and another process, grouping the processes into a process group based on the value, determining if the process group is executable in a memory associated with a processor, and associating the process group, if determined executable, with the memory associated with the processor.

Method And Apparatus For Two-Stage Packet Classification Using Most Specific Filter Matching And Transport Level Sharing

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US Patent:
20050083935, Apr 21, 2005
Filed:
Oct 20, 2003
Appl. No.:
10/690301
Inventors:
Michael Kounavis - New York NY, US
Alok Kumar - Santa Clara CA, US
Raj Yavatkar - Portland OR, US
Harrick Vin - Austin TX, US
International Classification:
H04L012/56
US Classification:
370392000, 370395300
Abstract:
A method and apparatus for two-stage packet classification, the two-stage packet classification scheme including a first stage and a second stage. In the first classification stage, a packet is classified on the basis of the packet's network path. In the second stage of classification, the packet is classified on the basis of one or more transport (or other) fields of the packet. Also disclosed are embodiments of most specific filter matching and transport level sharing, and either one or both of these techniques may be implemented in the two-stage classification method.

Service Scheduling

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US Patent:
20050086657, Apr 21, 2005
Filed:
Oct 21, 2003
Appl. No.:
10/691116
Inventors:
James Jason - Hillsboro OR, US
Erik Johnson - Portland OR, US
Harrick Vin - Austin TX, US
Jayaram Mudigonda - Austin TX, US
International Classification:
G06F009/46
US Classification:
718102000
Abstract:
A process, method, and system that examines a set of services to identify two or more parallel services performed by a common processor. A defined number of data elements are processed to simulate a data flow through the set of services. An element ratio is determined that defines the portion of data elements processed by each of the parallel services.

Inserting Instructions

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US Patent:
20060212874, Sep 21, 2006
Filed:
Dec 12, 2003
Appl. No.:
10/734457
Inventors:
Erik Johnson - Hillsboro OR, US
James Jason - Portland OR, US
Harrick Vin - Austin TX, US
International Classification:
G06F 9/46
US Classification:
718107000
Abstract:
In general, in one aspect, the disclosure describes a method of automatically inserting into a first thread instructions that relinquishes control of a multi-tasking processor to another thread will be concurrently sharing the processor.
Harrick M Vin from Austin, TX, age ~58 Get Report