Harlan R Isaak

6351029, Feb 26, 2002

May 19, 2000

09/574321

Harlan R. Isaak - Costa Mesa CA, 92626

H01L 2348

257688, 257698

A stackable integrated circuit chip package comprising a flex circuit. The flex circuit itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces, and a conductive pattern which is disposed on the bottom surface. The chip package further comprises a frame which is attached to the substrate of the flex circuit, and an integrated circuit chip which is at least partially circumvented by the frame and electrically connected to the conductive pattern. The substrate is wrapped about and attached to at least a portion of the frame such that the conductive pattern defines first and second portions which are each electrically connectable to another stackable integrated circuit chip package.

6404043, Jun 11, 2002

Jun 21, 2000

09/598343

Harlan R. Isaak - Costa Mesa CA

Dense-Pac Microsystems, Inc. - Garden Grove CA

H01L 2302

257686, 257685, 257777, 257723, 361829

A chip stack comprising at least two base layers, each of which includes a base substrate and a first conductive pattern disposed on the base substrate. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon. The interconnect frame is disposed between the base layers, with the second conductive pattern being electrically connected to the first conductive pattern of each of the base layers. Also included in the chip stack are at least two integrated circuit chips which are electrically connected to respective ones of the first conductive patterns. One of the integrated circuit chips is at least partially circumvented by the interconnect frame and at least partially covered by one of the base layers. The chip stack further comprises a transposer layer comprising a transposer substrate having a third conductive pattern disposed thereon. The first conductive pattern of one of the base layers is electrically connected to the third conductive pattern of the transposer layer.

6426240, Jul 30, 2002

Jun 25, 2001

09/888785

Harlan R. Isaak - Costa Mesa CA, 92626

H01L 2144

438106, 438109

A stackable integrated circuit chip package having a flex circuit. The flex circuit itself includes a flexible substrate having opposed, generally planar top and bottom surfaces, and a conductive pattern which is disposed on the bottom surface. The chip package further includes a frame which is attached to the substrate of the flex circuit, and an integrated circuit chip which is at least partially circumvented by the frame and electrically connected to the conductive pattern. The substrate is wrapped about and attached to at least a portion of the frame such that the conductive pattern defines first and second portions which are each electrically connectable to another stackable integrated circuit chip package.

6426549, Jul 30, 2002

Nov 3, 2000

09/706015

Harlan R. Isaak - Costa Mesa CA, 92626

H01L 23495

257686, 257685, 257692, 257723, 257779, 257736, 257737, 257738, 257780, 257781, 257784

A stackable flex circuit IC package includes a flex circuit comprised of a flexible base with a conductive pattern thereon, and wrapped around at least one end portion of a frame so as to expose the conductive pattern at the edge portion. An IC device is mounted within a central aperture in the frame, and is electrically coupled to the conductive pattern. The IC device is sealed in place within the frame with epoxy. A stack of the IC packages is assembled by disposing a conductive epoxy of anisotropic material between the conductive patterns at the edge portions of adjacent IC packages. Application of pressure in a vertical or Z-axis direction between adjacent IC packages completes electrical connections between the individual conductors of the conductive patterns of adjacent IC packages to interconnect the IC packages of the stack, while at the same time maintaining electrical isolation between adjacent conductors within each of the conductive patterns. The IC devices may comprise bare memory chips electrically coupled to the conductive pattern by wire bonds which are encapsulated in the epoxy together with the chip. Alternatively, where the IC devices comprise ball grid array (BGA) devices, such as chip scale packages, BGAs, flip chips, or the like, the matrix of balls or other conductive elements on the device are disposed within apertures ablated through the flexible base of the flex circuit where they are soldered to the conductive pattern.

6472735, Oct 29, 2002

Apr 5, 2001

09/826621

Harlan R. Isaak - Costa Mesa CA, 92626

H01L 2302

257686, 257777, 257685

A chip stack comprising at least two base layers, each of which includes a base substrate and a first conductive pattern disposed on the base substrate. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon. The interconnect frame is disposed between the base layers, with the second conductive pattern being electrically connected to the first conductive pattern of each of the base layers via an anisotropic epoxy. Also included in the chip stack are at least two integrated circuit chips which are electrically connected to respective ones of the first conductive patterns. One of the integrated circuit chips is at least partially circumvented by the interconnect frame and at least partially covered by one of the base layers. The chip stack further comprises a transposer layer comprising a transposer substrate having a third conductive pattern disposed thereon. The first conductive pattern of one of the base layers is electrically connected to the third conductive pattern of the transposer layer via an anisotropic epoxy.

6566746, May 20, 2003

Dec 14, 2001

10/017553

Harlan R. Isaak - Costa Mesa CA
Andrew C. Ross - Ramona CA
Glen E. Roeters - Huntington Beach CA

DPAC Technologies, Corp. - Garden Grove CA

H01L 2302

257685, 257686, 257777

A chip stack comprising at least one base layer including a base substrate having a first conductive pattern disposed thereon. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon which is electrically connected to the first conductive pattern of the base layer. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may each be electrically connected to the first conductive pattern of the base layer such that one of the integrated circuit chip packages is at least partially circumvented by the interconnect frame. Alternatively, one of the integrated circuit chip packages may be electrically connected to the first conductive pattern, with the remaining integrated circuit chip package being attached to the base substrate and at least partially circumvented by the interconnect frame such that the circumvented integrated circuit chip package and the second conductive pattern of the interconnect frame collectively define a composite footprint for the chip stack. A transposer layer may be included as a portion of each chip stack, with the transposer layer including a third conductive pattern specifically configured to provide a CSP-TSOP interface.

6514793, Feb 4, 2003

Jun 25, 2001

09/888792

Harlan R. Isaak - Costa Mesa CA

DPAC Technologies Corp. - Garden Grove CA

H01L 2148

438109, 438110, 438118, 438126, 438127

A stackable flex circuit IC package includes a flex circuit comprised of a flexible base with a conductive pattern thereon, and wrapped around at least one end portion of a frame so as to expose the conductive pattern to the edge portion. An IC device is mounted within a central aperture in the frame, and is electrically coupled to the conductive pattern. The IC device is sealed in place within the frame with epoxy. A stack of the IC packages is assembled by disposing a conductive epoxy of anisotropic material between the conductive patterns at the edge portions of adjacent IC packages. Application of pressure in a vertical or Z-axis direction between adjacent IC packages completes electrical connections between the individual conductors of the conductive patterns of adjacent IC packages to interconnect the IC packages of the stack, while at the same time maintaining electrical isolation between adjacent conductors within each of the conductive patterns.

6544815, Apr 8, 2003

Aug 6, 2001

09/922977

Harlan R. Isaak - Costa Mesa CA, 92626

H01L 2144

438109, 438107, 438108, 257686, 257777, 257778

A chip stack comprising at least two base layers, each of which includes a base substrate and a first conductive pattern disposed on the base substrate. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon. The interconnect frame is disposed between the base layers, with the second conductive pattern being electrically connected to the first conductive pattern of each of the base layers. Also included in the chip stack are at least two integrated circuit chips which are electrically connected to respective ones of the first conductive patterns. One of the integrated circuit chips is at least partially circumvented by the interconnect frame and at least partially covered by one of the base layers. The chip stack further comprises a transposer layer comprising a transposer substrate having a third conductive pattern disposed thereon. The first conductive pattern of one of the base layers is electrically connected to the third conductive pattern of the transposer layer.