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Hanxi Zhang Chen

from Palo Alto, CA
Age ~60
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Also known as:
Hanxi Z Chen, Hanxi Te Chen, Hanxi Zhang, Zhang Chen Hanxi, Xi Zhang Hanxi, I Chen
Phone and address:
761 De Soto Dr, Palo Alto, CA 94303
(650) 804-8086
Related to:
Xun LiuYi D Zhang, 55Yahua Liu, 63Yi Zhang, 51Nanyan Zhang, 49
Connected to:
Aiyu Chen, 33Allen C Chen, 73Aluna F Chen, 58Anna D Chen, 67Annamaria E Chen, 38Annice B Chen, 31Anthony Chen, 60Ava H Chen, 42Baofeng Chen, 40Barbara K Chen, 45

Hanxi Chen Phones & Addresses

  • 761 De Soto Dr, Palo Alto, CA 94303 (650) 804-8086
  • Antioch, CA
  • Pebble Beach, CA
  • Menlo Park, CA
  • Stockton, CA
  • Brentwood, CA
  • State College, PA
  • San Jose, CA
  • Highlands Ranch, CO

Business Records

Name / Title
Company / Classification
Phones & Addresses
Hanxi Chen
Jph Medical LLC
Medical Supplies
761 De Soto Dr, Palo Alto, CA 94303
12687 Mccartysville Pl, Saratoga, CA 95070

Publications

Us Patents

Efficient Device Debug System

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US Patent:
6472900, Oct 29, 2002
Filed:
Jun 4, 2001
Appl. No.:
09/874188
Inventors:
Deviprasad Malladi - Campbell CA
Shahid Ansari - Milpitas CA
Hanxi Chen - San Jose CA
Bidyut Sen - Milpitas CA
Steven Boyle - Santa Clara CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G01R 3126
US Classification:
324765, 257700
Abstract:
A method and system providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expos at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.

Efficient Debug Package Design

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US Patent:
62462520, Jun 12, 2001
Filed:
Jul 30, 1999
Appl. No.:
9/364563
Inventors:
Deviprasad Malladi - Campbell CA
Shahid Ansari - Milpitas CA
Hanxi Chen - San Jose CA
Bidyut Sen - Milpitas CA
Steven Boyle - Santa Clara CA
Assignee:
Sun Microsystems, Inc. - Palo Alto CA
International Classification:
G01R 3126
H01L 23053
US Classification:
324765
Abstract:
A method for providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expose at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.
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Hanxi Zhang Chen from Palo Alto, CA, age ~60 Get Report