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Guntram Konrad Wolski

from Soquel, CA
Age ~61

Guntram Wolski Phones & Addresses

  • 15 Suncrest Dr, Soquel, CA 95073 (831) 476-8857
  • 157 Hartford St, San Francisco, CA 94114
  • 159 Hartford St, San Francisco, CA 94114
  • McKinleyville, CA
  • Santa Cruz, CA
  • Aptos, CA
  • Sun Lakes, AZ
  • Orange Pk, FL
  • Richmond, VA
  • Watsonville, CA

Work

Company: Intel corporation Oct 2016 Position: Director, custom cpu product development, data center group

Education

School / High School: University of California, Berkeley 1983 to 1985 Specialities: Electrical Engineering, Computer Science

Skills

Asic • Physical Design • Verilog • Perl • Requirements Analysis

Industries

Semiconductors

Resumes

Resumes

Guntram Wolski Photo 1

Director, Custom Cpu Product Development, Data Center Group

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Intel Corporation
Director, Custom Cpu Product Development, Data Center Group

Cisco Oct 2014 - Oct 2016
Principal Engineer and Director Physical Implementation Team Leader

Cisco Feb 2005 - Oct 2014
Principal Engineer, Physical Implementation Team Leader, Enterprise Networking Group

Sunext Design 2004 - 2005
Physical Design Manager

Tau Networks 2001 - 2003
Cot and Methodology Technical Lead and Manager
Education:
University of California, Berkeley 1983 - 1985
University of California, Santa Cruz 1981 - 1983
Skills:
Asic
Physical Design
Verilog
Perl
Requirements Analysis

Publications

Us Patents

Built-In Self-Test Tri-State Architecture

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US Patent:
55131905, Apr 30, 1996
Filed:
Oct 28, 1991
Appl. No.:
7/783491
Inventors:
Peter A. Johnson - San Jose CA
Guntram K. Wolski - Watsonville CA
Assignee:
Sequoia Semiconductor, Inc. - Scotts Valley CA
International Classification:
G01R 102
US Classification:
371 225
Abstract:
A circuit architecture for driving a tri-state bus in a logic circuit that uses a built-in self-test (BIST) mechanism. The architecture includes tri-state drivers which have circuitry to inhibit other drivers from driving the bus when another driver is driving the bus. The architecture includes circuitry to pullup the bus or to allow the bus to retain the last state it was driven to when none of the drivers is driving the bus. This circuitry also drives the bus to a known state during testing of the logic circuit.

Method Of Making Single Layer Personalization

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US Patent:
52061841, Apr 27, 1993
Filed:
Nov 15, 1991
Appl. No.:
7/792586
Inventors:
Joanne M. Allen - Scotts Valley CA
Richard B. Hansen - Bonny Doon CA
Guntram K. Wolski - Watsonville CA
Keith R. Venes - Aptos CA
Assignee:
Sequoia Semiconductor, Inc. - Scotts Valley CA
International Classification:
H01L 2160
US Classification:
437 51
Abstract:
A process for implementing logic units using base cells and implementing an electrical connection between the logic units in a gate array. The process includes determining a connection path between the base cells and connecting the base cells at the second metalization layer using a portion of the first metalization layer. This is possible due to the gate array having vertical first metalization layer segments of the first metalization layer positioned vertically in the channel between the rows of base cells, wherein each of the vertical segments has vias in the insulation layer between the first metalization layer and the second metalization layer at its endpoints for connecting the metalization layers. Similarly, the individual transistors which comprise the base cell are coupled using the second metalization layer to implement a specific logic unit.
Guntram Konrad Wolski from Soquel, CA, age ~61 Get Report