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Greg S Dykema

from Santa Clara, CA
Age ~69
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Also known as:
Greg Steven Dykema, Greg I Dykema, Gregory S Dykema, Gregory Te Dykema
Phone and address:
3102 Arthur Ct, Santa Clara, CA 95051
(408) 961-8239
Related to:
Barbara A Forster, 87Patricia Dykema, 65Megan DykemaLauren Dykema, 39
Connected to:
Carin L Dykema, 73Darcie J Dykema, 65Elizabeth J Dykema, 63Jane A Dykema, 83Karen R Dykema, 63Kate L Dykema, 36Kurt R Dykema, 76Adrian B Dykeman, 42Bonnie N Dykeman, 68Dawn A Dykeman, 65

Greg Dykema Phones & Addresses

  • 3102 Arthur Ct, Santa Clara, CA 95051 (408) 961-8239 (408) 243-4539
  • 302 Arthur Ct, Santa Clara, CA 95051
  • Sunnyvale, CA

Resumes

Resumes

Greg Dykema Photo 1

Greg Dykema

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Location:
Santa Clara, CA
Industry:
Warehousing
Work:
Vishay Siliconix Jan 2001 - Jul 2016
Material Handler and Warehousing and Shipping Receiving and Chemical Technician 3
Education:
San Jose State University
Bachelors, Social Sciences West Valley College
Associates, Social Sciences
Skills:
Organization Skills
Problem Solving
Languages:
English
Greg Dykema Photo 2

Engineering

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Location:
Santa Clara, CA
Industry:
Computer Hardware
Work:
Stealth Mode Startup Company
Engineering
Opelin Oct 2017 - May 2019
System Architect
Opelin May 2013 - Sep 2017
Asic Architect
Opelin Dec 2010 - May 2013
System Technical Lead For the Storeserv 7000 Family
3Par Jul 2001 - Feb 2011
Principal Engineer
Education:
University of Michigan 1987 - 1989
Master of Science, Masters, Computer Science, Engineering, Computer Science and Engineering Calvin University 1983 - 1987
Bachelors, Bachelor of Science, Computer Science, German
Skills:
Asic
Debugging
Hardware Architecture
System Architecture
Hardware
Storage
Processors
Computer Architecture
Testing
Semiconductors
Program Management
Device Drivers
Simulations
Ethernet
Architecture
Embedded Systems
Perl
Manufacturing
Computer Hardware
Functional Verification
Engineering Management
Software Development
Linux
Python
Pcie

Publications

Us Patents

Mechanisms For Synchronizing Data Transfers Between Non-Uniform Memory Architecture Computers

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US Patent:
8244930, Aug 14, 2012
Filed:
May 5, 2010
Appl. No.:
12/774280
Inventors:
Greg L. Dykema - Redwood City CA, US
David H. Bassett - San Jose CA, US
Joel L. Lach - Fremont CA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 3/00
G06F 13/00
US Classification:
710 22, 710 28, 710 31, 710 33, 710 35
Abstract:
A first node includes a DMA engine for transferring data specified by a sequence of control blocks to a second node. When a control block does not require synchronization between memories, the DMA engine sends an end of transfer (EOT) message after the last datum, increments an EOT counter, and processes the next control block. When a control block requires synchronization and the EOT counter is at zero, the DMA engine sends an EOT with a flag after the last datum, increments the EOT counter, and waits for the EOT counter to return to zero before processing the next control block. A memory controller at the second node detects the EOT with or without a flag and generates an EOT acknowledgement with or without a flag. When a link interface at the second node detects the EOT acknowledgement with a flag, it sends an interrupt to a local processor complex.

Trainable Link

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US Patent:
7802153, Sep 21, 2010
Filed:
Dec 7, 2006
Appl. No.:
11/608241
Inventors:
Michel P. Cekleov - Mountain View CA, US
Christopher Cheng - Cupertino CA, US
Greg L. Dykema - Redwood City CA, US
David Chu - Santa Clara CA, US
Assignee:
3PAR, Inc. - Fremont CA
International Classification:
G01R 31/28
H04L 7/00
H04B 17/00
G06F 11/00
US Classification:
714712, 714821, 375224, 375354, 370241
Abstract:
A method is provided to align clock and data signals over a source-synchronous link. The method includes sending header data and a default clock signal over the link. The header indicates a start of a training packet and the default clock signal ensures that the header is received without error. The method further includes providing a long clock pulse, phase shifting the clock signal during the long clock pulse, and thereafter sending training data and the clock signal over the link. The above steps are repeated until the training data are received with error. At that point, the phase shift of the clock signal is saved as a boundary of an optimal alignment. The above steps are then repeated with the clock signal shifted in a different direction. Once another boundary is located, the boundary midpoint is saved as the phase shift that provides the optimal alignment.

Isbn (Books And Publications)

Science and Engineering on the Commodore 64

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Author

Greg Dykema

ISBN #

0916439097

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Greg S Dykema from Santa Clara, CA, age ~69 Get Report