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Glenn C Narvaez

from Livermore, CA
Age ~52
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Also known as:
Glenn Narvaez Calderon, Glenn C Nervaez
Phone and address:
5850 Cedarwood Cmn, Livermore, CA 94550
Connected to:
Allyssa N Narvaez, 51Alvin J Narvaez, 41Amaury Narvaez, 31Brittany Narvaez, 34Carlos I Narvaez, 42Catalina R Narvaez, 73Daniela M Narvaez, 30Darcia F Narvaez, 72Debora A Narvaez, 67Don Narvaez, 46

Glenn Narvaez Phones & Addresses

  • 5850 Cedarwood Cmn, Livermore, CA 94550
  • Redwood City, CA
  • Palo Alto, CA
  • Beverly Hills, FL
  • Hernando, FL
  • Farmington, NM
  • El Paso, TX
  • Alameda, CA

Work

Company: Pleasanton tutoring Mar 2016 Position: Academic tutor

Education

Degree: Master of Science, Masters School / High School: Stanford University 1994 to 1996 Specialities: Materials Science, Engineering

Skills

Semiconductors • Product Development • Engineering Management • Design of Experiments • Semiconductor Industry • Failure Analysis • Spc • Cross Functional Team Leadership • Fmea • Manufacturing • Reliability • R&D • Manufacturing Engineering • Product Engineering • Process Engineering • Engineering Support • Computer Building • System Design • Assembly Drawings • Production Development • Product Management • Management • Engineering • Program Management • Six Sigma • Lean Manufacturing • Technical Writing • Technical Documentation • Continuous Improvement • Root Cause Analysis • Design of Experiments • Failure Mode and Effects Analysis

Languages

English

Interests

Arts and Culture

Emails

g***[email protected]

Industries

Semiconductors

Resumes

Resumes

Glenn Narvaez Photo 1

Academic Tutor

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Pleasanton Tutoring
Academic Tutor
The Crucible
Volunteer
Entrepreneurial Consulting/Management
Consultant
Stats Chippac Jan 2006 - Sep 2008
Engineering Systems Manager
Stats Chippac Aug 2004 - Dec 2006
Senior Manager, Ww Tpm
Education:
Stanford University 1994 - 1996
Master of Science, Masters, Materials Science, Engineering Massachusetts Institute of Technology 1990 - 1994
Bachelors, Bachelor of Science, Materials Science, Engineering
Skills:
Semiconductors
Product Development
Engineering Management
Design of Experiments
Semiconductor Industry
Failure Analysis
Spc
Cross Functional Team Leadership
Fmea
Manufacturing
Reliability
R&D
Manufacturing Engineering
Product Engineering
Process Engineering
Engineering Support
Computer Building
System Design
Assembly Drawings
Production Development
Product Management
Management
Engineering
Program Management
Six Sigma
Lean Manufacturing
Technical Writing
Technical Documentation
Continuous Improvement
Root Cause Analysis
Design of Experiments
Failure Mode and Effects Analysis
Interests:
Arts and Culture
Languages:
English

Publications

Us Patents

Chip Scale And Land Grid Array Semiconductor Packages

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US Patent:
6551859, Apr 22, 2003
Filed:
Feb 22, 2001
Appl. No.:
09/791437
Inventors:
Shaw Wei Lee - Curpertino CA
Thanh Lequang - San Jose CA
Wayne W. Lee - San Jose CA
Glenn Narvaez - Redwood City CA
William Jeffery Schaefer - San Jose CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2148
US Classification:
438112, 438123, 438124, 438126, 438127, 29827, 29841, 29855, 29856
Abstract:
Techniques for improving the manufacture and structure of leadframe chip scale packages and land grid array packages are described. One aspect of the invention pertains to a method for patterning a conductive substrate, which is utilized to form a packaged semiconductor device, wherein a metallic barrier layer and a second metallic layer are utilized as an etching resist. A method, according to another aspect of the invention pertains to covering a metallic barrier layer and second metallic layer with a etch resistant cap such that the etch resistant cap is used as a etching resist. In another aspect of the present invention, a method for treating a conductive leadframe with a CZ treatment is disclosed. In yet another aspect of the present invention, techniques relating to locking grooves within the studs of a studded leadframe are disclosed.

Substrate For Use In Semiconductor Packaging

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US Patent:
6396135, May 28, 2002
Filed:
Dec 21, 2000
Appl. No.:
09/748309
Inventors:
Glenn C. Narvaez - Redwood City CA
Shaw Wei Lee - Cupertino CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2302
US Classification:
257678, 257783, 438106
Abstract:
A number of techniques and substrate arrangements are described that working individually and in common have been found to significantly improve the environmental resistance of the resulting package. In one aspect, conductive pads (referred to herein as landing pads) on the top surface of a substrate are slightly undercut. This permits molding material applied during later packaging to flow into the undercut regions to help improve adhesion between the substrate and the molding material. In another aspect, metallic die attach pads formed on the substrate are patterned to provide better adhesion between the substrate and a solder mask that covers the die attach pads. More specifically, the metallic die attach pads are patterned to have a number of opening defined therein that leave corresponding portions of the substrate exposed. In substrates where a solder mask is applied over the die attach pad, the openings permit the solder mask to adhere directly to the substrate panel in the openings thereby strengthening the attachment of the solder mask to the substrate. In still another aspect, elongated slots are provided in the solder mask such that the slots expose one or more rows of adjacent landing pads instead of simply the landing pads themselves.
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Glenn C Narvaez from Livermore, CA, age ~52 Get Report