US Patent:
20110113219, May 12, 2011
Inventors:
Gholam Reza Golshan - Los Gatos CA, US
George W. Harvey - Stanford CA, US
Allen Nejah - San Jose CA, US
Assignee:
SUNMAN ENGINEERING, INC. - San Jose CA
International Classification:
G06F 13/00
G06F 15/76
G06F 9/06
US Classification:
712 30, 710316, 712E09003
Abstract:
A system includes first and second processors, first and second graphics processing units (GPUs), one or more peripheral devices, a switch matrix, and processor-readable memory. The switch matrix comprises programmable data paths between the processors, the GPUs, and the peripheral devices. Software encoded in the process-readable memory includes a first operating system (OS) executed by the first processor, a second OS executed by the second processor, a matrix scheduling engine, and a media interface switch (MIS) engine. The first OS boots faster than the second OS. The matrix scheduling engine runs on both OSs and configures the data paths in the switch matrix to couple the processors and the GPUs, and to couple the processors and the peripheral devices. The MIS engine runs on the operating systems, detects presence of the peripheral devices, and configures the data paths in the switch matrix to couple the processors and the peripheral devices.