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Gerard Pepenella Phones & Addresses

  • 27 Frontier Trl, Manorville, NY 11949 (631) 878-1856 (631) 878-7629
  • Blandon, PA
  • Thornton, CO
  • Denver, CO
  • 27 Frontier Trl, Manorville, NY 11949

Work

Position: Clerical/White Collar

Education

Degree: High school graduate or higher

Business Records

Name / Title
Company / Classification
Phones & Addresses
Gerard J. Pepenella
KSR PARTNERS, INC
27 Frontier Trl, Manorville, NY 11949

Publications

Us Patents

Use Of Dual Hysteresis Modes In Determining A Loss Of Signal Output Indication

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US Patent:
6489803, Dec 3, 2002
Filed:
Sep 7, 2001
Appl. No.:
09/949483
Inventors:
Philip David Steiner - Nashua NH
Gerard Pepenella - Manorville NY
Assignee:
Silicon Laboratories, Inc. - Austin TX
International Classification:
A03K 1716
US Classification:
326 31, 327205, 326 21
Abstract:
A loss of signal condition is evaluated for an input data stream according to a signal strength threshold level. The signal strength threshold level is determined according to a supplied loss of signal (LOS) threshold level. Two hysteresis modes are used to ensure the hysteresis at low LOS threshold levels is sufficient. The first mode uses hysteresis for the signal strength threshold level that is proportional to the LOS threshold level when the LOS threshold level is above a predetermined level. The second mode employs fixed hysteresis for the signal strength threshold level when the LOS threshold level is below the predetermined level. The hysteresis provides a signal strength threshold level that has a greater magnitude on deassertion of a loss of signal indication than on assertion of the loss of signal indication.

Method And Apparatus For Generating A Clock Signal In Holdover Mode

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US Patent:
7148753, Dec 12, 2006
Filed:
Jun 4, 2003
Appl. No.:
10/453990
Inventors:
Bruno W. Garlepp - Milpitas CA, US
Gerard Pepenella - Manorville NY, US
Assignee:
Silicon Laboratories Inc. - Austin TX
International Classification:
H03L 7/00
US Classification:
331 2, 331 17, 331 1 A, 331 49, 327156, 327159
Abstract:
A first phase-locked loop circuit that includes a crystal oscillator, receives a reference clock signal and supplies a first phase-locked loop output signal based on the reference clock during normal operational mode and a stored value in holdover mode. A second phase-locked loop circuit receives the first phase-locked loop output signal and utilizes the first phase-locked loop output signal when generating an output clock in holdover mode. The second phase-locked loop utilizes the first phase-locked loop output signal during operation in the holdover mode to generate the output clock and utilizes the reference clock during normal operational mode to generate the output clock. Alternatively, the second phase-locked loop utilizes the first phase-locked loop output signal both during operation in the holdover mode and during normal operational mode to generate the output clock. The first phased-lock loop circuit may include a low pass filter coupled to the loop filter, which supplies a low pass filtered signal to the crystal oscillator in holdover mode. The first phased-lock loop circuit may include a low pass filter and a delay circuit coupled to the loop filter, which supply a delayed and low pass filtered signal to the crystal oscillator in holdover mode.

Distributed Switch Architecture Including A Growth Input/Output Bus Structure

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US Patent:
7436824, Oct 14, 2008
Filed:
Feb 17, 2005
Appl. No.:
11/059816
Inventors:
Gerard Pepenella - Manorville NY, US
Assignee:
Silicon Laboratories Inc. - Austin TX
International Classification:
H04L 12/50
H04Q 11/00
US Classification:
370386
Abstract:
Multiple integrated circuits (ICs) are connected via growth inputs, into a network configuration, e. g. a ring network or a mesh network, to form a communications switch. Each IC includes additional growth inputs beyond those needed to form the switch. These growth inputs can be used to add additional functionality, e. g. protection or transmultiplexing, to the switch.

Data Optimized Codec

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US Patent:
6356593, Mar 12, 2002
Filed:
Apr 28, 1998
Appl. No.:
09/067895
Inventors:
Lynn Emery Ditty - Northampton PA
Donald Lars Duttweiler - Rumson NJ
Gerard Joseph Pepenella - Blandon PA
Dewayne Alan Spires - Plaistow NH
Assignee:
Lucent Technologies Inc. - Murray Hill NJ
International Classification:
H04B 1404
US Classification:
375242, 375222, 455557
Abstract:
Quantization noise, introduced into data transmission when analog signals are translated into PCM code using the logarithmic conversion of -law or A-law rules necessary to accommodate the transmission of voice signals, limits the maximum attainable speed of data transmission. However, when the PCM code signals represent data (rather than voice signals), linear conversion of analog data signals into the PCM code would avoid such logarithmic quantization noise. To signal the translating codec that a digital modem call is being made, the digital modem allocates one or more of the least significant bit positions of the code representing the 2100 Hz answer-tone-with-phase-reversal (specified in ITU-T Recommendation G. 165) to send a repetitive pattern âP â to signal to the associated codec that a digital modem connection has been made. When the codec detects the P pattern it will linearly convert analog data signals into PCM code, thereby reducing the introduction of logarithmic quantization noise.
Gerard J Pepenella from Manorville, NY, age ~66 Get Report