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Gerald P Miaille

from Gilbert, AZ
Age ~50
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Also known as:
Gerald Paul Miaille, Gerald P Mialle, Jerald Miaille
Related to:
Larisa Miaille
Connected to:
Edward Miakisz, 70Nathan R Miakisz, 46David J Mial, 32Donna M Mial, 70Tyler J Mial, 38Harry D Miale, 73Raymond G Miale, 83Carolyn M Miales, 72Matthew L Mialki, 41Richard J Miami, 75

Gerald Miaille Phones & Addresses

  • Gilbert, AZ
  • 2130 Erie St, Chandler, AZ 85224
  • 4324 S Gold Ct, Chandler, AZ 85248
  • Tempe, AZ
  • Phoenix, AZ
  • Maricopa, AZ
  • 1412 W Indigo Dr, Chandler, AZ 85248

Work

Company: Freescale semiconductor Position: Analog design manager at freescale semiconductor

Education

Degree: Master of Business Administration, Masters School / High School: Washington State University - Carson College of Business

Skills

Design • Engineering • Analog

Industries

Semiconductors

Resumes

Resumes

Gerald Miaille Photo 1

Analog Design Manager At Freescale Semiconductor

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Location:
Phoenix, AZ
Industry:
Semiconductors
Work:
Freescale Semiconductor
Analog Design Manager at Freescale Semiconductor
Education:
Washington State University - Carson College of Business
Master of Business Administration, Masters
Skills:
Design
Engineering
Analog

Publications

Us Patents

Accumulated Current Counter And Method Thereof

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US Patent:
7358743, Apr 15, 2008
Filed:
Apr 27, 2006
Appl. No.:
11/380479
Inventors:
Gerald P. Miaille - Chandler AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G01R 31/08
G01R 19/00
G01N 27/416
H02J 7/00
US Classification:
324522, 324 7611, 324426, 320132
Abstract:
An accumulated current counter () includes a sense resistor () configured for being coupled in series between an electronic circuit () and a power source (). The sense resistor is further for use in sensing a voltage (V) across the sense resistor as a function of a current (Ibatt) provided via the power source. An incremental counter () is coupled to the sense resistor for incrementally counting an amount of current, corresponding to an average value of charge Q, going (i) into or (ii) out of the power source. A register () accumulates a representation of the incrementally counted current. In one embodiment, the representation of incrementally counted current corresponds to a remaining power source life in hours and minutes.

Methods And Apparatus For A Multi-Mode Analog-To-Digital Converter

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US Patent:
7379002, May 27, 2008
Filed:
Dec 15, 2006
Appl. No.:
11/639676
Inventors:
Zhou Zhixu - Gilbert AZ, US
Julian Aschieri - Tempe AZ, US
Gerald P. Miaille - Chandler AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H03M 3/00
US Classification:
341143, 341155
Abstract:
A multi-mode analog-to-digital converter includes a delta-sigma analog-to-digital converter circuit configured to receive the analog input and produce a digital bit-stream associated therewith, the delta-sigma analog-to-digital converter including at least one integrator configured to reset to an initial state in response to a reset signal A digital filter circuit is configured to receive the digital bit-stream and produce two filtered outputs derived from the digital bit-stream. During one mode (e. g. , a DC mode) the delta-sigma analog-to-digital converter circuit is configured to receive the reset signal and produce the digital bit-stream for a predetermined number of clock cycles, and the digital output corresponds to the first filtered output. In another mode (e. g. , an AC mode), the delta-sigma analog-to-digital converter is configured to continuously produce the bit-stream, and the digital output corresponds to the second filtered output.

Calibrating A Digital-To-Analog Converter

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US Patent:
7443323, Oct 28, 2008
Filed:
Jan 10, 2007
Appl. No.:
11/651858
Inventors:
Christian J. Rotchford - Austin TX, US
Brandt Braswell - Chandler AZ, US
Jiangbo Gan - Gilbert AZ, US
Michael L. Gomez - Tempe AZ, US
Gerald P. Miaille - Chandler AZ, US
Boris V. Razmyslovitch - Chandler AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H03M 1/10
US Classification:
341120, 341118, 341144, 341145
Abstract:
Methods and corresponding systems for calibrating a digital-to-analog converter include selecting first and second code regions in the digital-to-analog converter, wherein the first and second code regions are separated by a boundary. Thereafter a waveform sequence is input into the digital-to-analog converter, wherein the waveform sequence has a zero offset at the boundary. Then a relative compensation value between the first and second code regions is adjusted to reduce a distortion in an output of the digital-to-analog converter. A magnitude of a third harmonic distortion of the waveform sequence can be used to measure distortion in the output. Adjusting the relative compensation can include converting the output of the digital-to-analog converter to a digital sequence, filtering the digital sequence, and measuring a harmonic distortion in the digital sequence.

Digital Audio Amplifiers, Electronic Systems, And Methods

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US Patent:
7579908, Aug 25, 2009
Filed:
Aug 25, 2007
Appl. No.:
11/845035
Inventors:
Gerald P. Miaille - Chandler AZ, US
Julian Aschieri - Tempe AZ, US
Zhou Zhixu - Gilbert AZ, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H03F 3/38
US Classification:
330 10, 330251
Abstract:
An embodiment of an electronic system includes a digital audio amplifier having a continuous time modulator adapted to generate a difference signal between an audio bitstream and a feedback signal, and to perform a modulation process on the difference signal to generate an input pulse modulated signal, a class D output stage adapted to receive, quantize, and amplify the input pulse modulated signal to generate an output pulse modulated signal, and a feedback path adapted to provide the output pulse modulated signal as the feedback signal to the continuous time modulator. Another embodiment includes a class AB output stage adapted to receive and amplify an input digital audio signal to generate an analog output signal, and circuitry adapted to enable the digital audio amplifier to be configured to enable the class AB output stage and to disable the class D output stage.

Low Drop-Out Voltage Regulator

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US Patent:
20050225306, Oct 13, 2005
Filed:
Feb 12, 2003
Appl. No.:
10/504909
Inventors:
Ludovic Oddoart - Frouzins, FR
Gerald Miaille - Tempe AZ, US
International Classification:
G05F001/40
US Classification:
323274000
Abstract:
A low drop-out voltage regulator having a pass device (Mp), an error amplifier (M-M) and a double regulation loop including DC feedback loop (R, R) and an AC feedback loop (Rf, Cf) including a high pass filter (Cf). Combining these two loops creates an ultra low frequency internal pole which makes the regulator stable substantially independent of the output bypass capacitor's value. This provides the following advantages: allows the use of very low bypass capacitors; allows to extend the PSRR frequency behavior; allows an increase in the regulator's efficiency (reduced power consumption on heavy loads).

Antenna Usage As A User Interface

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US Patent:
20210133399, May 6, 2021
Filed:
Nov 5, 2019
Appl. No.:
16/675088
Inventors:
- San Diego CA, US
Nicolas Graube - Cambridge, GB
Murray Jarvis - Cambridge, GB
Andrew John Laister - Cambridge, GB
Gerald Miaille - Chandler AZ, US
International Classification:
G06K 7/10
G06F 3/01
H04R 1/10
H01Q 1/27
Abstract:
Methods, systems, and devices for wireless communications are described. Generally, the described techniques provide for identifying, by a wearable device, a baseline antenna impedance value, detecting one or more sensor inputs, monitoring for a variation in antenna impedance from the baseline antenna impedance value, identifying a user gesture (e.g., based at least in part on the detected sensor inputs and the variation from the baseline antenna impedance value) at least one user gesture, and updating an operational status of the device based on the detected user gesture.
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Gerald P Miaille from Gilbert, AZ, age ~50 Get Report