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Gerald G Fagerness

from Lewiston, MN
Age ~74
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Also known as:
Gerald Gregory Fagerness, Jerald Fagerness
Phone and address:
490 Harrison St, Lewiston, MN 55952
Related to:
Amber Guillen, 24Humberto Guillen, 83Janet Vanbriesen, 71Adam J Vanbriesen, 39Nicole M Dewar, 51Janet K Fagerness, 73Adam J Fagerness, 39Mark G Lowry, 46Travis J Fagerness, 37Colleen A Fagerness, 72Sean J Dewar, 51Celeste R Fagerness, 60Katelyn M Dewar, 27Bradley W Elsing, 73
Connected to:
Jesen A Fagerness, 51Jon D Fagerness, 76Stanley J Fagerness, 76Jan M Fagerquist, 72Timothy L Fagerson, 57Aaron E Fagerstrom, 48Gary W Fagerstrom, 56Rosa Fagerstrom, 45Starr K Fagerstrom, 65Amanda Fagg, 34

Gerald Fagerness Phones & Addresses

  • 490 Harrison St, Lewiston, MN 55952
  • Winona, MN
  • 212 5Th St, Rochester, MN 55901
  • 1894 41St St, Rochester, MN 55901
  • Mazeppa, MN
  • Circle Pines, MN

Work

Position: Consulting engineer

Industries

Computer Hardware

Resumes

Resumes

Gerald Fagerness Photo 1

Consulting Engineer

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Location:
P/O Box 112, Lewiston, MN
Industry:
Computer Hardware
Work:

Consulting Engineer

Publications

Us Patents

Method And Apparatus To Verify Non-Deterministic Results In An Efficient Random Manner

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US Patent:
7523367, Apr 21, 2009
Filed:
Jun 30, 2005
Appl. No.:
11/171783
Inventors:
Gerald G. Fagerness - Winona MN, US
Terry J. Opie - Rochester MN, US
Paul E. Schardt - Rochester MN, US
David E. Wood - Dennison MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 29/00
US Classification:
714719, 714739, 714742
Abstract:
The present invention is directed to a system, method and article of manufacture for testing and design verification of hardware devices by providing for random accesses to the registers of a device under test. Such random accesses may more closely resemble actual accesses to the registers of a device during normal operation, thus providing a more thorough test.

Methods And Apparatus For Indexing Memory Of A Network Processor

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US Patent:
8213428, Jul 3, 2012
Filed:
Jul 24, 2003
Appl. No.:
10/625954
Inventors:
Gerald G. Fagerness - Rochester MN, US
Kerry C. Imming - Rochester MN, US
Brian M. McKevett - Rochester MN, US
James F. Mikos - Rochester MN, US
Tolga Ozguner - Rochester MN, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H04L 12/56
US Classification:
370392, 3703957
Abstract:
A method is provided for address mapping in a network processor. The method includes the steps of (1) determining a port number of a port that receives a data cell; (2) determining a virtual path identifier and a virtual channel identifier for the data cell; and (3) creating a first index based on at least one of the port number, the virtual path identifier and the virtual channel identifier. The method further includes (1) accessing one of a plurality of entries stored in a first on-chip memory using the first index; (2) creating a second index based on the accessed entry of the first on-chip memory; and (3) accessing an entry of a second memory based on the second index. Numerous other aspects are provided.

Method And Apparatus For Performing Microcode Paging During Instruction Execution In An Instruction Processor

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US Patent:
57969728, Aug 18, 1998
Filed:
Jan 14, 1997
Appl. No.:
8/783614
Inventors:
David C. Johnson - Roseville MN
Douglas A. Fuller - Eagan MN
Kenneth L. Engelbrecht - Blaine MN
Gregory A. Marlan - San Jose CA
Ronald G. Arnold - Apple Valley MN
Gerald G. Fagerness - Mazeppa MN
Assignee:
Unisys Corporation - Blue Bell PA
International Classification:
G06F 924
US Classification:
395384
Abstract:
Method and apparatus for performing microcode paging during instruction execution in an instruction processor. In a preferred embodiment an instruction processor is provided that includes both a microcode ROM and a microcode RAM. The microcode ROM stores the current release of the microcode for the computer system, and the microcode RAM stores microcode patch instructions. During instruction execution, the present invention selects between the output of the microcode ROM and the microcode RAM, depending on whether the instruction requires a patch microcode instruction. If the desired microcode patch instruction is not stored in the microcode RAM, the instruction processor is temporarily interrupted and the desired microcode patch instruction or a group of microcode patch instructions are written, or paged, into the microcode RAM.

Programmable Sram And Dram Cache Interface With Preset Access Priorities

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US Patent:
61516643, Nov 21, 2000
Filed:
Jun 9, 1999
Appl. No.:
9/329134
Inventors:
John Michael Borkenhagen - Rochester MN
Gerald Gregory Fagerness - Mazeppa MN
John David Irish - Rochester MN
David John Krolak - Dodge Center MN
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G06F 1318
US Classification:
711150
Abstract:
A cache interface that supports both Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM) is disclosed. The cache interface preferably comprises two portions, one portion on the processor and one portion on the cache. A designer can simply select which RAM he or she wishes to use for a cache, and the cache controller interface portion on the processor configures the processor to use this type of RAM. The cache interface portion on the cache is simple when being used with DRAM in that a busy indication is asserted so that the processor knows when an access collision occurs between an access generated by the processor and the DRAM cache. An access collision occurs when the DRAM cache is unable to read or write data due to a precharge, initialization, refresh, or standby state. When the cache interface is used with an SRAM cache, the busy indication is preferably ignored by a processor and the processor's cache interface portion. Additionally, the disclosed cache interface allows speed and size requirements for the cache to be programmed into the interface.

Fault Isolating To A Block Of Rom

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US Patent:
58319883, Nov 3, 1998
Filed:
Jan 23, 1997
Appl. No.:
8/788111
Inventors:
Gerald G. Fagerness - Mazeppa MN
Assignee:
Unisys Corporation - Blue Bell PA
International Classification:
G11C 2900
US Classification:
371 212
Abstract:
Apparatus for fault isolating errors in memory elements. A test "Signature" word is obtained by successively manipulating all of the words in a memory block. A first embodiment uses serial processing and a second embodiment uses parallel processing. In either process, prior to test, a derived signature is provided, which is the same as the resulting test signature for each block if no error is detected, and which are stored in test order prior to testing. In either embodiment, after each test signature word is obtained from a block of data, the test signature word is compared bit for bit with the corresponding derived Signature word, and if the two are not identical, an error is indicated. Any block addresses which contain errors are marked in a Fault Address RAM which can be read by external equipment to avoid the use of the faulty blocks.

Array Self-Test Fault Tolerant Programmable Threshold Algorithm

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US Patent:
58621512, Jan 19, 1999
Filed:
Jan 23, 1997
Appl. No.:
8/788109
Inventors:
Gerald G. Fagerness - Mazeppa MN
Assignee:
Unisys Corporation - Blue Bell PA
International Classification:
G01R 3128
US Classification:
371 225
Abstract:
The present invention relates to a method and apparatus for a greater-than-zero, programmable array fault tolerance used during built-in self-test (BIST) operation. In a first embodiment, a single BIST engine is provided for selected memory elements existing on a die within a logic array. The fault tolerance is set by scanning a register to a number between 0 and 7 to determine the number of faults that are tolerated before the array is considered unusable. After all of the selected memory elements are tested, the die is deemed usable if the total error count does not exceed the fault tolerance contained in the scannable register. Alternatively, each of the selected memory elements on the die may have a dedicated BIST engine. If fault tolerance is enabled for a particular BIST engine, the die will be deemed unusable if more than one fault is detected for the particular memory element associated with the dedicated BIST engine, or alternatively, if the total number of faults detected by all of the BIST engines exceeds the a predetermined fault tolerance number.
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Gerald G Fagerness from Lewiston, MN, age ~74 Get Report