Georgios Palaskas

7250815, Jul 31, 2007

Feb 25, 2004

10/786677

Stewart S. Taylor - Beaverton OR, US
Ian A. Rippke - Ithaca NY, US
Georgios Palaskas - Portland OR, US

Intel Corporation - Santa Clara CA

H03F 1/36

330107, 330149

An apparatus and a system, as well as a method and an article, may include detecting an indication of an amplifier output signal amplitude and responsively adjusting the amplifier input signal phase to reduce a change in the phase of the output signal.

7333423, Feb 19, 2008

Mar 31, 2004

10/815138

Georgios Palaskas - Portland OR, US
Ashoke Ravi - Hillsboro OR, US
Jeyanandh K. Paramesh - Hillsboro OR, US
Richard B. Nicholls - Banks OR, US
Krishnamurthy Soumyanath - Portland OR, US

Intel Corporation - Santa Clara CA

H04J 11/00
H04B 1/38
H04B 1/10
H04B 1/26

370210, 375219, 455303, 455323

Phase and amplitude offsets of a multicarrier transceiver may be reduced by measuring receiver amplitude and phase mismatches of receiver radio-frequency (RF) circuitry by performing a fast Fourier transform (FFT) on a receiver calibration signal.

7605625, Oct 20, 2009

Oct 7, 2007

11/868500

Stefano Pellerano - Beaverton OR, US
Georgios Palaskas - Portland OR, US

Intel Corporation - Santa Clara CA

H03L 7/08
H03L 7/06

327158, 327161, 327271, 327277

System and method of calibrating delay mismatch for high-spectral purity applications. For example, a method includes measuring the delay of one delay element at a time in a fixed topology by moving a time reference generated by an auxiliary delay-locked loop. The auxiliary DLL may have a replica structure of the primary DLL being calibrated. The calibration method uses one output clock signal of the primary DLL and measures delay mismatch using a reference phase previously measured using the same topology. The calibration method takes into account all delay mismatches in the topology up to the primary DLL output clock signal, including any delay generated by an associated multiplexer.

7609792, Oct 27, 2009

Mar 1, 2005

11/069172

Georgios Palaskas - Portland OR, US
Ashoke Ravi - Hillsboro OR, US
Richard B. Nicholls - Banks OR, US
Keith A. Holt - El Dorado Hills CA, US
Stanley K. Ling - Rocklin CA, US

Intel Corporation - Santa Clara CA

H04B 7/10

375347, 370335, 370503, 375219, 375345, 375376, 375267, 455333, 455450, 4555501, 327199, 327259

A multichip transceiver operates as part of a multiple-input multiple-output communication system. First receiver circuitry on a first integrated circuit processes radio-frequency (RF) signals received from a first signal source, and second receiver circuitry on a second integrated circuit processes RF signals received from a second signal source. Clock-signal generating circuitry provides clock signals through phase-matched paths to the first and second receiver circuitry.

7653147, Jan 26, 2010

Aug 17, 2005

11/206447

Georgios Palaskas - Portland OR, US
Stewart S. Taylor - Beaverton OR, US
Hasnain Lakdawala - Hillsboro OR, US

Intel Corporation - Santa Clara CA

H04L 25/03

375297, 375295

An apparatus for transmitter control is disclosed. The apparatus includes an analog circuit designed to operate on at least a portion of a communications signal to be wirelessly transmitted, based at least in part on a control signal. The apparatus includes a lookup table coupled to the analog circuit, with the lookup table designed to output the control signal based at least in part on the communications signal, or one or more measured metrics of the communications signal. Embodiments of the present invention include, but are not limited to, methods encompassing the operations described above, as well as subsystems and systems designed to operate in the above described manner.

7657232, Feb 2, 2010

Sep 18, 2006

11/522599

Georgios Palaskas - Portland OR, US
Stefano Pellerano - Beaverton OR, US
Ashoke Ravi - Hillsboro OR, US

Intel Corporation - Santa Clara CA

H04B 17/00
H04B 1/00
H04B 15/00
H04B 1/06

455 6711, 455 6713, 455275, 455 631

Embodiments of methods and means for calibrating a linearization characteristic within an RF transceiver system are provided. Such embodiments generally include extracting a portion of an output signal and frequency shifting or translating that signal by a predetermined value. The frequency shifted signal is then summed or otherwise introduced into a receiver signal pathway where it is analyzed by digital signal processing or other means to determine if linearization distortion is present. Linearization calibration of a power amplifier, a low-noise amplifier and/or other functionality within the system can then be performed in an automatic, reliable and ongoing manner.

7856212, Dec 21, 2010

Aug 7, 2007

11/835330

Stefano Pellerano - Beaverton OR, US
Rajarshi Mukhopadhyay - Richardson TX, US
Georgios Palaskas - Portland OR, US

Intel Corporation - Santa Clara CA

H04B 1/40
H04K 3/00

455 76, 4551803, 455260, 327147, 375376

Embodiments of a millimeter-wave phase-locked loop with an injection-locked frequency divider (ILFD) are generally described herein. Other embodiments may be described and claimed. In some embodiments, the ILFD uses a quarter-wavelength transmission line. A method of calibrating an ILFD is also provided to allow the ILFD to operate at or near the center of its locking range for each of a plurality of VCO oscillating frequency bands.

8222966, Jul 17, 2012

Sep 10, 2010

12/879152

Ashoke Ravi - Hillsboro OR, US
Paolo Madoglio - Beaverton OR, US
Marian Verhelst - Beaverton OR, US
Georgios Palaskas - Portland OR, US

Intel Corporation - Santa Clara CA

H03C 3/02
H03K 7/06
H04B 1/02

332144, 375271, 375302, 455 42, 455110

A device article and method for an open loop calibrated phase wrapping phase modulator. A tapped delay line may provide a coarse resolution for one or more phases of a signal. A phase multiplexer may receive one or more coarse phases from the tapped delay line and select a coarse phase to send to the digitally controlled delay line. A digitally controlled delay line may provide a fine resolution to the coarse phase from the phase multiplexer.