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George E Ganschow

from Boulder Creek, CA
Age ~70
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Also known as:
Gorge Ganschow, Ganschow Gorge
Phone and address:
191 Crows Nest Dr, Big Basin, CA 95006
(831) 338-4418
Related to:
Melroy V Brook, 84Sarah C Marsh, 42Dezarae Karam, 45Phillip D Karam, 41Matthew KaramKaren K Murray, 63
Connected to:
Cheryl E Ganschow, 53David W Ganschow, 53Randall S Ganschow, 69Shane P Ganschow, 44Timothy C Ganschow, 53Lynne D Gansebom, 69Eric K Gansel, 44Klaus J Gansel, 90Lawrence V Gansel, 38Lori A Gansel, 50

George Ganschow Phones & Addresses

  • 191 Crows Nest Dr, Boulder Creek, CA 95006 (831) 338-4418
  • Santa Cruz, CA
  • Trabuco Canyon, CA
  • Cameron Park, CA
  • Puyallup, WA
  • San Jose, CA
  • 191 Crows Nest Dr, Boulder Creek, CA 95006 (831) 246-1377

Work

Position: Machine Operators, Assemblers, and Inspectors Occupations

Education

Degree: Associate degree or higher

Emails

g***[email protected]

Publications

Us Patents

Reducing Base Resistance Of A Bjt By Forming A Self Aligned Silicide In The Single Crystal Region Of The Extrinsic Base

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US Patent:
51399610, Aug 18, 1992
Filed:
Apr 2, 1990
Appl. No.:
7/503498
Inventors:
Alan G. Solheim - Puyallup WA
Bamdad Bastani - Danville CA
James L. Bouknight - Puyallup WA
George E. Ganschow - Trabuco Canyon CA
Bancherd Delong - Puyallup WA
Rajeeva Lahri - Puyallup WA
Steve M. Leibiger - Graham WA
Christopher S. Blair - Puyallup WA
Rick C. Jerome - Puyallup WA
Madan Biswal - Puyallup WA
Tad Davies - Puyallup WA
Vida Ilderem - Puyallup WA
Ali A. Iranmanesh - Federal Way WA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2133
US Classification:
437 33
Abstract:
A high performance bipolar transistor and a method of fabrication. Base resistance is reduced by a self-aligned silicide formed in the single-crystal region of the extrinsic base, thereby eliminating the polysilicon to single-crystal contact resistance as well as shunting the resistance of the single-crystal extrinsic base region. Oxide from the sidewall of the polysilicon local interconnection is selectively removed prior to silicide formation. Therefore, selected sidewalls of the poly interconnect layer also becomes silicided. This results in significant reductions in resistance of the interconnection, particularly for sub-micron geometries. Improved techniques for forming field oxide regions and for forming base regions of bipolar transistors are also disclosed.

Bipolar Transistor With Diffusion Compensation

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US Patent:
52890244, Feb 22, 1994
Filed:
Apr 7, 1993
Appl. No.:
8/044560
Inventors:
George E. Ganschow - Trabuco Canyon CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2972
H01L 2712
H01L 29167
US Classification:
257592
Abstract:
A bipolar transistor having a base intrinsic region, collector region, and emitter region. The emitter region, collector region, and base intrinsic region each having at least a portion thereof adjacent to an oxide isolation region. The base intrinsic region having a diffusion compensation region therein abutting the oxide isolation region. The diffusion compensation region compensates for the intrinsic concentrations segregating during oxidation, and also compensates for oxide charge contribution to the base region. The additional dopant in the compensation region results in only a small increase in the desired BJT performance and adds minimal complexity in manufacturing. The invention results in the controlled placement of dopants near the "birds's beak" between the emitter and base providing I. sub. CEO leakage current reduction at the emitter edge without affecting the bulk of the active intrinsic base.

Method Of Making Polysilicon Schottky Clamped Transistor And Vertical Fuse Devices

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US Patent:
52121020, May 18, 1993
Filed:
Jun 5, 1992
Appl. No.:
7/894403
Inventors:
Ali A. Iranmanesh - Federal Way WA
George E. Ganschow - Trabuco Canyon CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21265
US Classification:
437 31
Abstract:
An improved method for fabricating polysilicon Schottky clamped transistors and vertical fuse devices in the same semiconductor structure is disclosed. The resulting structure yields an improved Schottky clamped transistor and vertical fuse device. The improved Schottky transistor has a silicide rectifying contact between the base and collector of the transistor, the vertical fuse is provided with a direct contact between an aluminum contact metal and a polysilicon emitter contact.

Polysilicon Schottky Clamped Transistor And Vertical Fuse Devices

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US Patent:
51444046, Sep 1, 1992
Filed:
Aug 22, 1990
Appl. No.:
7/571346
Inventors:
Ali A. Iranmanesh - Federal Way WA
George E. Ganschow - Trabuco Canyon CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2948
H01L 2972
H01L 2904
H01L 2702
US Classification:
357 51
Abstract:
An improved method for fabricating polysilicon Schottky clamped transistors and vertical fuse devices in the same semiconductor structure is disclosed. The resulting structure yields an improved Schottky clamped transistor and vertical fuse device. The improved Schottky transistor has a silicide rectifying contact between the base and collector of the transistor, the vertical fuse is provided with a direct contact between an aluminum contact metal and a polysilicon emitter contact.

Inversion Implant Isolation Process

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US Patent:
54828740, Jan 9, 1996
Filed:
Nov 19, 1993
Appl. No.:
8/154891
Inventors:
George E. Ganschow - Trabuco Canyon CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21265
H01R 2122
US Classification:
437 31
Abstract:
A method for improving the performance of a walled emitter bipolar-junction transistor and the improved walled emitter bipolar junction transistor resulting therefrom are disclosed. The method involves the incorporation of a p-type dopant, preferably boron, at the intersection of the isolation oxide and the emitter-base region. The selective implantation does not affect the transistor's function in any significant way, does not complicate the fabrication process to any significant degree and eliminates known problems of intrinsic base boron segregation and oxide charges in known walled emitter bipolar junction transistors.

Vertical Fuse Device

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US Patent:
54364965, Jul 25, 1995
Filed:
Feb 14, 1994
Appl. No.:
8/195901
Inventors:
Rick C. Jerome - Puyallup WA
Ronald P. Kovacs - Mountain View CA
George E. Ganschow - Trabuco Canyon CA
Lawrence K. C. Lam - Kent WA
James L. Bouknight - Puyallup WA
Frank Marazita - San Jose CA
Brian McFarlane - Campbell CA
Ali Iranmanesh - Federal Way WA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2948
H01L 2972
US Classification:
257529
Abstract:
A vertical fuse structure including a lightly-doped shallow emitter 30 provides improved fusing characteristics. The structure includes a buried collector 14, an overlying base 30, and an emitter 44 above the base 30. In one preferred embodiment, the emitter 44 extends about 0. 2 microns from the upper surface and has a dopant concentration of about 8. times. 1019 atoms of arsenic per cubic centimeter at the surface. A lightly doped base region 30 extends for about 0. 46 microns below the emitter 44 to the collector 14. The upper surface of emitter 44 includes a metal contact 60. Heating the metal 60/emitter 44 interface to its eutectic melting point using a current or voltage pulse causes the aluminum to short through the emitter 44 to the base 30. Shorting the emitter programs the fuse. A second preferred embodiment uses polysilicon as an interconnecting medium.

Self-Aligned Silicided Base Bipolar Transistor And Resistor And Method Of Fabrication

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US Patent:
50454838, Sep 3, 1991
Filed:
Apr 2, 1990
Appl. No.:
7/503340
Inventors:
Bancherd DeLong - Puyallup WA
Christopher S. Blair - Puyallup WA
George E. Ganschow - Puyallup WA
Thomas S. Crabb - Puyallup WA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21328
US Classification:
437 31
Abstract:
A bipolar transistor and resistor are provided. Fabrication includes using a high temperature oxide to form sidewall spacers for the transistor contacts and/or to overlay the resistor portion of the device. Deposition of the HTO is combined with dopant drive-in so that fewer total steps are required. The process is compatible with MOS technology so that the bipolar transistor and resistor can be formed on a substrate along with MOS devices.
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George E Ganschow from Boulder Creek, CA, age ~70 Get Report