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Geoffrey S Gongwer

from Auburn, CA
Age ~67
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Also known as:
Geoffrey Steven Gongwer, Geoff S Gongwer, Geoffrey R
Phone and address:
12010 Mont Vista Dr, Auburn, CA 95603
Related to:
Giovanna J Fox, 53Laura Gongwer, 34Jamene P Gongwer, 64Nora L Allen, 92Gary L Gongwer, 61Kelsey M Gongwer, 43Shawn J Gongwer, 32Gayla E Gongwer, 69
Connected to:
Susan K Gongwer, 76Christine D Goni, 53Ricardo A Goni, 49Rudy P Goni, 57Catherine A Gonia, 64David J Gonick, 55Michael L Gonidakis, 51Simon P Gonifas, 43Ashlee R Gonigam, 39Ella N Gonik, 65

Geoffrey Gongwer Phones & Addresses

  • 12010 Mont Vista Dr, Auburn, CA 95603
  • Santa Clara, CA
  • Sunnyvale, CA
  • 5328 Beechwood Ln, Los Altos, CA 94024 (650) 988-1536
  • Campbell, CA
  • San Jose, CA
  • Mountain View, CA

Resumes

Resumes

Geoffrey Gongwer Photo 1

Geoffrey Gongwer

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Location:
United States

Publications

Us Patents

Method And System For Generation And Distribution Of Supply Voltages In Memory Systems

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US Patent:
6434044, Aug 13, 2002
Filed:
Feb 16, 2001
Appl. No.:
09/788120
Inventors:
Geoffrey Steven Gongwer - Los Altos CA
Kevin M. Conley - San Jose CA
Chi-Ming Wang - Fremont CA
Yong Liang Wang - Saratoga CA
Raul Adrian Cernea - Santa Clara CA
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
G11C 1604
US Classification:
36518518, 36518511, 365226
Abstract:
Techniques for producing and supplying various voltage levels within a memory system having multiple memory blocks (e. g. , memory chips) are described. The various voltage levels can be produced by voltage generation circuitry (e. g. , charge pump and/or regulator circuitry) within the memory system. The various voltage levels can be supplied to the multiple memory blocks through a power bus. According to one aspect, charge pump and/or regulator circuits are provided within at most one of the memory blocks of a memory system (unless back-ups are provided for fault tolerance), and a power bus is used to distribute the generated voltage levels to other of the memory blocks. According to another aspect, a memory controller generates multiple supply voltage levels that are distributed (e. g. , via a power bus) to each of the memory blocks.

System And Method For Achieving Fast Switching Of Analog Voltages On Large Capacitive Load

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US Patent:
6486715, Nov 26, 2002
Filed:
Apr 2, 2001
Appl. No.:
09/825615
Inventors:
Geoffrey S. Gongwer - Los Altos CA
Shahzad Khalid - Union City CA
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
H03K 17687
US Classification:
327111, 327108
Abstract:
Driver ( ) and method are provided for driving capacitive load ( ) that achieve an improved response time without increasing power consumption of the driver. Driver ( ) has load buffer ( ) with an input ( ) for receiving an input voltage (VIN), and an output for coupling an output voltage (V ) to load. V is driven between a first voltage level (V ) and a second voltage level (V ) in response to changes in V. Driver ( ) also has reserve circuit ( ) with capacitor ( ), reserve buffer ( ), switch ( ) for coupling the capacitor to capacitive load ( ) and controller ( ) for operating the switch. Reserve buffer ( ) has an input ( ) for receiving an input voltage (V ), and an output ( ) for coupling an output voltage (V ) to capacitor ( ) to charge the capacitor. Controller ( ) is configured to operate switch ( ) to couple capacitor ( ) to capacitive load ( ) when V is being driven between V and V.

Writable Tracking Cells

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US Patent:
6538922, Mar 25, 2003
Filed:
Sep 27, 2000
Appl. No.:
09/671793
Inventors:
Shahzad B. Khalid - Union City CA
Daniel C. Guterman - Fremont CA
Geoffrey S. Gongwer - Los Altos CA
Richard Simko - Los Altos Hills CA
Kevin M. Conley - San Jose CA
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
G11C 1604
US Classification:
36518503, 3651852
Abstract:
The present invention presents several techniques for using writable tracking cells. Multiple tracking cells are provided for each write block of the memory. These cells are re-programmed each time the user cells of the associated write block are written, preferably at the same time, using the same fixed, global reference levels to set the tracking and user cell programmed thresholds. The threshold voltages of the tracking cells are read every time the user cells are read, and these thresholds are used to determine the stored logic levels of the user cells. In one set of embodiments, populations of one or more tracking cells are associated with different logic levels of a multi-state memory. These tracking cell populations may be provided for only a subset of the logic levels. The read points for translating the threshold voltages are derived for all of the logic levels based upon this subset.

Error Management For Writable Tracking Storage Units

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US Patent:
6678192, Jan 13, 2004
Filed:
Nov 2, 2001
Appl. No.:
10/053339
Inventors:
Geoffrey S. Gongwer - Los Altos CA
Shahzad B. Khalid - Union City CA
Daniel C. Guterman - Fremont CA
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
G11C 1606
US Classification:
3651852, 36518509, 36518524, 36518529
Abstract:
A memory system (e. g. , memory card) having error management for stored levels (e. g. , reference levels) used in discrimination of logic levels for data storage units providing data storage is disclosed. The stored levels can be stored in predetermined storage units (e. g. , writable tracking storage units) in the memory system. The memory system is typically a non-volatile memory product or device that provides binary or multi-state data storage.

Non-Volatile Memory With Improved Programming And Method Therefor

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US Patent:
6738289, May 18, 2004
Filed:
Feb 26, 2001
Appl. No.:
09/793370
Inventors:
Geoffrey Gongwer - Los Altos CA
Daniel C. Guterman - Fremont CA
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
G11C 1604
US Classification:
36518512, 36518511
Abstract:
Non-volatile memory that has non-volatile charge storing capability such as EEPROM and flash EEPROM is programmed by a programming system that applies to a plurality of memory cells in parallel. Enhanced performance is achieved by programming each cell to its target state with a minimum of programming pulses using a data-dependent programming voltage. Further improvement is accomplished by performing the programming operation in multiphase where each successive phase is executed with a finer programming resolution such as employing a programming voltage with a gentler staircase waveform. These features allow rapid and accurate convergence to the target states for the group of memory cells being programmed in parallel, thereby allowing each cell to store several bits of information without sacrificing performance.

Efficient Read, Write Methods For Multi-State Memory

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US Patent:
6751129, Jun 15, 2004
Filed:
May 21, 2002
Appl. No.:
10/152536
Inventors:
Geoffrey S. Gongwer - Los Altos CA
Assignee:
Sandisk Corporation - Sunnyvale CA
International Classification:
G11C 700
US Classification:
36518905, 365 51, 36518505
Abstract:
Methods and apparatus for efficiently writing data to and reading data from multi-state memory cells. According to one aspect of the present invention, a memory system includes a first storage element, a data source, a first element, a second element, and a ripple clock. The data source provides a plurality of bits to be stored in the first storage element, and the first element receives a first bit from the data source, and also clocks the first bit into the second element. The first element then receives a second bit of the plurality of bits from the data source substantially while the first bit is being stored into the first storage element. The ripple clock enables access to the first element and the second element such that the first bit and the second bit may be pipelined.

Increasing The Effectiveness Of Error Correction Codes And Operating Multi-Level Memory Systems By Using Information About The Quality Of The Stored Data

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US Patent:
6751766, Jun 15, 2004
Filed:
May 20, 2002
Appl. No.:
10/152137
Inventors:
Daniel C. Guterman - Fremont CA
Stephen Jeffrey Gross - Cupertino CA
Geoffrey S. Gongwer - Los Altos CA
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
G11C 2900
US Classification:
714736
Abstract:
The quality of data stored in a memory system is assessed by different methods, and the memory system is operated according to the assessed quality. The data quality can be assessed during read operations. Subsequent use of an Error Correction Code can utilize the quality indications to detect and reconstruct the data with improved effectiveness. Alternatively, a statistics of data quality can be constructed and digital data values can be associated in a modified manner to prevent data corruption. In both cases the corrective actions can be implemented specifically on the poor quality data, according to suitably chosen schedules, and with improved effectiveness because of the knowledge provided by the quality indications. These methods can be especially useful in high-density memory systems constructed of multi-level storage memory cells.

Noise Reduction Technique For Transistors And Small Devices Utilizing An Episodic Agitation

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US Patent:
6850441, Feb 1, 2005
Filed:
Jan 18, 2002
Appl. No.:
10/052924
Inventors:
Nima Mokhlesi - Los Gatos CA, US
Daniel C. Guterman - Fremont CA, US
Geoffrey S. Gongwer - Los Altos CA, US
Assignee:
SanDisk Corporation - Sunnyvale CA
International Classification:
G11C 1604
US Classification:
36518519, 36518521, 36518509
Abstract:
The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e. g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.
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Geoffrey S Gongwer from Auburn, CA, age ~67 Get Report