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Gary N Neben

from Boulder, CO
Age ~65
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Also known as:
Gary J Neben
Phone and address:
775 Grape Ave, Boulder, CO 80304
(303) 417-0072
Related to:
Jane KesslerJanet Yanowitz, 61Jyoti Cameron, 52Joseph E Cameron, 67Alexana Roshko, 64Alexander A Neben, 26Bernice NebenJames S Cameron
Connected to:
Derek A Neben, 36Adina M Nebenzahl, 51James B Nebenzahl, 73Ryan D Nebera, 42Erik V Nebergall, 71Lindsey Nebergall, 41Marie C Nebergall, 79Michelle L Nebergall, 46Mark E Neberman, 72Robert J Nebert, 100

Gary Neben Phones & Addresses

  • 775 Grape Ave, Boulder, CO 80304 (303) 417-0072 (303) 449-3753
  • Burlington, MA
  • Belmont, MA
  • Boston, MA
  • 775 Grape Ave, Boulder, CO 80304 (303) 449-3753

Work

Company: Huawei Sep 2008 Position: Staff engineer

Education

School / High School: Massachusetts Institute of Technology 1978 to 1983

Skills

Simulation • Design • Consumer Electronics

Emails

g***[email protected]

Industries

Consumer Electronics

Resumes

Resumes

Gary Neben Photo 1

Staff Engineer

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Location:
Denver, CO
Industry:
Consumer Electronics
Work:
Huawei since Sep 2008
Staff Engineer
RFMD May 2007 - May 2008
Staff Engineer
Toshiba Jun 1997 - Sep 2006
Senior Staff
Education:
Massachusetts Institute of Technology 1978 - 1983
Skills:
Simulation
Design
Consumer Electronics

Business Records

Name / Title
Company / Classification
Phones & Addresses
Gary Neben
President
Advanced Architecture Systems Inc
Architectural Services
775 Grape Ave, Boulder, CO 80304
(303) 449-3753

Publications

Wikipedia

D'Gary

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1993 trat D'Gary neben seinen Kollegen Dama und Rossy beim Festival Internationale in Lafayette/Louisiana auf. Mit Dama und zwei Musikern aus der Band von ...

Us Patents

Single-Wire Serial Interface

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US Patent:
20110185215, Jul 28, 2011
Filed:
Jan 25, 2011
Appl. No.:
13/013625
Inventors:
Gary Neben - Boulder CO, US
Assignee:
FUTUREWEI TECHNOLOGIES, INC. - Plano TX
International Classification:
G06F 1/12
US Classification:
713401
Abstract:
A circuit comprising a single-wire serial interface (SWSI), a delay module coupled to the SWSI and operable to introduce a delay during a data transmission, the delay being dependent on a local clock (LC) associated with the circuit, wherein the delay enables the circuit to synchronize the data transmission with a device coupled to the SWSI based on the LC.

Fault Tolerant Memory System Which Utilizes Data From A Shadow Memory Device Upon The Detection Of Erroneous Data In A Main Memory Device

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US Patent:
56196423, Apr 8, 1997
Filed:
Dec 23, 1994
Appl. No.:
8/363132
Inventors:
Michael E. Nielson - Broomfield CO
William A. Brant - Boulder CO
Gary Neben - Boulder CO
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 1100
US Classification:
39518204
Abstract:
A fault tolerant memory system is disclosed which includes a main memory device, storing data and an associated error detecting code, and a shadow memory device, storing data corresponding to the data stored in the main memory. A multiplexer, selectively couples data from either the main memory device or the shadow memory device to an output terminal in response to a control signal. A controller reads the data and associated error detecting code from the main memory device and the corresponding data from the shadow memory device, and generates the multiplexer control signal such that the multiplexer couples data from the shadow memory device to the output terminal if the data from the main memory device is not the same as the data from the shadow memory device and the error detecting code indicate an error in the data from the main memory device, and otherwise couples the data from the main memory device to the output terminal.

Fault Tolerant Memory System

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US Patent:
59058544, May 18, 1999
Filed:
Sep 26, 1996
Appl. No.:
8/721522
Inventors:
Michael E. Nielson - Broomfield CO
William A. Brant - Boulder CO
Gary Neben - Boulder CO
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F11/00
US Classification:
39518204
Abstract:
A fault tolerant memory system is disclosed which includes a main memory device, storing data and an associated error detecting code, and a shadow memory device, storing data corresponding to the data stored in the main memory. A multiplexer, selectively couples data from either the main memory device or the shadow memory device to an output terminal in response to a control signal. A controller reads the data and associated error detecting code from the main memory device and the corresponding data from the shadow memory device, and generates the multiplexer control signal such that the multiplexer couples data from the shadow memory device to the output terminal if the data from the main memory device is not the same as the data from the shadow memory device and the error detecting code indicate an error in the data from the main memory device, and otherwise couples the data from the main memory device Lo the output terminal.

Method And Apparatus For Fault Tolerant Fast Writes Through Buffer Dumping

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US Patent:
55487114, Aug 20, 1996
Filed:
Dec 22, 1994
Appl. No.:
8/363655
Inventors:
William A. Brant - Boulder CO
Gary Neben - Boulder CO
Michael E. Nielson - Broomfield CO
David C. Stallmo - Boulder CO
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 1100
US Classification:
39518203
Abstract:
An array controller including a DATA-RAM and a SHADOW-RAM. Both the DATA-RAM and the SHADOW-RAM are coupled to a first and second memory interface. Each memory interface has the ability to independently communicate the contents of the SHADOW-RAM over a controller-controller data link to at least one other similar array controller. The memory interface also interfaces the DATA-RAM and the SHADOW-RAM to a CPU, the data storage units of the RAID system, and the controller processor. Write data received from the CPU is stored in the two independent memories in order to ensure that pending Write data (i. e. , Write data that has not yet been written to the RAID system, including any copyback cache device) will not be lost. In addition, the two memory interfaces provide redundant access routes which allow Write data to be retrieved by another array controller if the controller processor fails. A backup power source is provided to ensure that power will be available to at least one of the two memories such that the data that has been received within the controller will always be accessible.
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Gary N Neben from Boulder, CO, age ~65 Get Report