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Gary A Brist

from Yamhill, OR
Age ~57
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Also known as:
Gary Birst
Phone and address:
8300 Highway 240, Yamhill, OR 97148
(503) 662-3889
Related to:
Jessica BristEric R Brist, 28Kaylee L BristKimberly D Brist, 53Mary O Brist, 81Logan A Brist, 26Lyle E Brist, 81Sharon L Brist, 56Lonnie E Brist, 55Brett A Brist, 29
Connected to:
Roger Brist, 64Bobby L Brister, 67Brian A Brister, 54Charles L Brister, 63Claude H Brister, 79Davalene E Brister, 49Jim Brister, 66Jordan T Brister, 38La V Brister, 63Lindsay Brister, 39

Gary Brist Phones & Addresses

  • 8300 Highway 240, Yamhill, OR 97148 (503) 662-3889
  • West Lafayette, IN
  • Forest Grove, OR
  • Libby, MT
  • Bozeman, MT
  • Newberg, OR

Publications

Us Patents

Power-Ground Plane Partitioning And Via Connection To Utilize Channel/Trenches For Power Delivery

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US Patent:
6747216, Jun 8, 2004
Filed:
Feb 4, 2002
Appl. No.:
10/068229
Inventors:
Gary A. Brist - Yamhill OR
Gary Baxter Long - Aloha OR
Daryl A. Sato - Beaverton OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H05K 111
US Classification:
174262, 174255, 174261, 174266, 361792, 361795
Abstract:
An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.

Waveguide In A Printed Circuit Board And Method Of Forming The Same

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US Patent:
6882762, Apr 19, 2005
Filed:
Sep 27, 2001
Appl. No.:
09/963637
Inventors:
Gary A. Brist - Yamhill OR, US
Carlos Mejia - Portland OR, US
William O. Alger - Portland OR, US
Gary B. Long - Aloha OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G02B006/12
US Classification:
385 14, 385129
Abstract:
A method is provided for forming a waveguide in a printed circuit board. This may include forming a trench in a printed circuit board substrate and forming at least one metalized surface along the trench. A metalized capping surface may be provided over the trench so as to form the waveguide structure.

Array Socket With A Dedicated Power/Ground Conductor Bus

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US Patent:
6916183, Jul 12, 2005
Filed:
Mar 4, 2003
Appl. No.:
10/379844
Inventors:
William O. Alger - Portland OR, US
Gary B. Long - Aloha OR, US
Gary A. Brist - Yamhill OR, US
Carlos Mejia - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01R012/00
US Classification:
439 69
Abstract:
An apparatus for receiving a microchip and having a conductor buses therein. A top surface of the apparatus receives the microchip while the bottom surface is to mount to a circuit board. A plurality of pin receptacles pass through the top surface to receive a corresponding plurality of microchip pins of the microchip. The conductor bus resides at least in part between the top surface and the bottom surface and is electrically coupled to a first plurality of the plurality of the pin receptacles.

Power Delivery Apparatus, Systems, And Methods

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US Patent:
6992899, Jan 31, 2006
Filed:
Mar 21, 2003
Appl. No.:
10/394841
Inventors:
William Alger - Portland OR, US
Gary Long - Aloha OR, US
Gary Brist - Yamhill OR, US
Carlos Mejia - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H05K 7/06
US Classification:
361767, 361768, 361783, 174260, 174261, 174262, 257691
Abstract:
An apparatus and system, as well as fabrication methods therefor, may include a conductor attached to a carrier to bridge a contact field defined by a circuit that can be mounted to a circuit board.

Printed Circuit Board Trace Routing Method

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US Patent:
7022919, Apr 4, 2006
Filed:
Jun 30, 2003
Appl. No.:
10/610147
Inventors:
Gary A. Brist - Yamhill OR, US
Gary B. Long - Aloha OR, US
William O. Alger - Portland OR, US
Dennis J. Miller - Sherwood OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H05K 1/16
US Classification:
174260, 174256, 174261, 174255, 716 15
Abstract:
An I/O routing pattern method is disclosed, for use with heterogeneous printed circuit boards (PCBs), such as those embedded with a reinforcement material, for example, a fiberglass weave. Traces are routed on the PCB so as to reduce sensitivity to changes in the dielectric constant (D), which are brought about by the strands of reinforcement material contained within the PCB laminate. The method minimizes the local variations, such as the D, time of flight, and capacitance variations, that are observed with traditional routing methods on heterogeneous PCBs.

Conductor Trace Design To Reduce Common Mode Cross-Talk And Timing Skew

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US Patent:
7043706, May 9, 2006
Filed:
Mar 11, 2003
Appl. No.:
10/387291
Inventors:
Gary A. Brist - Yamhill OR, US
Gary B. Long - Aloha OR, US
William O. Alger - Portland OR, US
Carlos Mejia - Portland OR, US
Bryce Horine - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 17/50
US Classification:
716 6, 716 15
Abstract:
A method and apparatus for reducing timing skew between conductor traces. A dielectric medium made of a resin reinforced with a fabric is provided. The fabric includes a first plurality of yarns running parallel to a first axis and a second plurality of yarns running parallel to a second axis. The first plurality of yarns are separated by a first weave pitch and the second plurality of yarns separated by a second weave pitch. At least two conductor traces are formed on the dielectric medium. The conductor traces are positioned on the dielectric medium such that the conductor traces each have substantially similar effective dielectric constants.

Photo-Thermal Induced Diffusion

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US Patent:
7064063, Jun 20, 2006
Filed:
Jul 9, 2003
Appl. No.:
10/617107
Inventors:
Gary A. Brist - Yamhill OR, US
Gary B. Long - Aloha OR, US
Daryl A. Sato - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/44
US Classification:
438661, 438662, 438692
Abstract:
Formation of a mixed-material composition through diffusion using photo-thermal energy. The diffusion may be used to create electrically conductive traces. The diffusion may take place between material layers on one of a package substrate, semiconductor substrate, substrate for a printed circuit board (PCB), or other multilayered substrate. The photo-thermal energy may be supplied by various devices, for example a YAG laser device, COlaser device, or other energy source.

Photo-Thermal Induced Diffusion

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US Patent:
7145243, Dec 5, 2006
Filed:
Jul 9, 2003
Appl. No.:
10/616748
Inventors:
Gary A. Brist - Yamhill OR, US
Gary B. Long - Aloha OR, US
Daryl A. Sato - Beaverton OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 21/348
H01L 23/52
H01L 29/40
US Classification:
257762, 257692, 257693, 257738, 257737, 257E21584, 257E23148, 257E21347, 427553, 427554, 427555, 427402, 428644, 428646, 428647, 428614
Abstract:
Formation of a mixed-material composition through diffusion using photo-thermal energy. The diffusion may be used to create electrically conductive traces. The diffusion may take place between material layers on one of a package substrate, semiconductor substrate, substrate for a printed circuit board (PCB), or other multi-layered substrate. The photo-thermal energy may be supplied by various devices, for example a YAG laser device, COlaser device, or other energy source.
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Gary A Brist from Yamhill, OR, age ~57 Get Report