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Galen G Kerber

from Lafayette, CO
Age ~62
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Related to:
Lenore L KerberHannah J Kerber, 27
Connected to:
Anne R Kerber, 60Benjamin H Kerber, 90Carol A Kerber, 60Cheryl S Kerber, 73Danell E Kerber, 48David A Kerber, 41Donna B Kerber, 63Erich J Kerber, 49Erin L Kerber, 50George F Kerber, 84

Galen Kerber Phones & Addresses

  • 10221 Arapahoe Rd, Lafayette, CO 80026 (303) 437-9051
  • Broomfield, CO
  • Northglenn, CO
  • Boston, MA
  • Newmarket, NH
  • Louisville, CO
  • 10221 Arapahoe Rd, Lafayette, CO 80026

Resumes

Resumes

Galen Kerber Photo 1

Fpga Design Engineer

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Location:
Lafayette, CO
Industry:
Aviation & Aerospace
Work:
Oracle since Feb 2010
Principal Hardware Engineer
Sun Microsystems Jun 2007 - Feb 2010
Design Verification Engineer
Quantum Corporation Nov 2002 - May 2007
ASIC and Design Engineer
Benchmark Storage Innovations (Benchmark Tape Systems) Jan 2001 - Nov 2002
ASIC and Design Engineer
Storage Technology Corporation (StorageTek) Mar 1993 - Dec 2000
Hardware Design Engineer
Education:
University of New Hampshire 1986 - 1992
MS, Electrical Engineering Massachusetts Institute of Technology 1980 - 1985
BS, Electrical Engineering and Computer Science
Skills:
Verilog
Debugging
Asic
Embedded Systems
Fpga
Hardware Architecture
Field Programmable Gate Arrays
Firmware
Application Specific Integrated Circuits
Microprocessors
Systemverilog
Testing
Management
Vhdl
Storage
Electronics
Rtl Design
C
Galen Kerber Photo 2

Galen Kerber

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Publications

Us Patents

Data Compression With Selective Encoding Of Short Matches

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US Patent:
7215259, May 8, 2007
Filed:
Jul 11, 2005
Appl. No.:
11/179080
Inventors:
Galen G. Kerber - Lafayette CO, US
Jeffrey A. Riley - Westminster CO, US
Bijan Eskandari-Gharnin - Littleton CO, US
Assignee:
Quantum Corporation - San Jose CA
International Classification:
H03M 7/34
US Classification:
341 51, 341106
Abstract:
A method and apparatus for encoding a sequence of input data into a sequence of coded data, where the coded data is represented as literal data, as single-character references to recent input data, and as a references to one or more past input data. The references may be fixed in length or variable in length. The references may include an indication of a match offset and/or an indication of a match length.

Method And Apparatus For Implementing Error Correction Coding In A Random Access Memory

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US Patent:
7676730, Mar 9, 2010
Filed:
Dec 29, 2005
Appl. No.:
11/322446
Inventors:
Rodger D. Haugan - Broomfield CO, US
Galen G. Kerber - Lafayette CO, US
David P. Haldeman - Broomfield CO, US
Assignee:
Quantum Corporation - San Jose CA
International Classification:
G11C 29/00
H03M 13/00
US Classification:
714769, 714766
Abstract:
Apparatuses and methods for utilizing error correction code in a data buffer or data storage device. In one variation, a single memory device is utilized to store both the data and the associated error correction code. The data and the associate error correction codes are stored on separate memory banks on the memory device. The error correction code may be consolidated into one or more regions on the memory device to improve the utilization of the available memory space on the memory device. In addition, by utilizing separate memory banks to store the data and the associated error correction code, the data and the error correction code can be accessed in an overlapping manner.

Extending Lock-In Range Of A Pll Or Dll

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US Patent:
20060291082, Dec 28, 2006
Filed:
Jun 23, 2005
Appl. No.:
11/166437
Inventors:
Steve Bounds - Broomfield CO, US
Jay Harker - Broomfield CO, US
Galen Kerber - Lafayette CO, US
International Classification:
G11B 5/09
US Classification:
360051000
Abstract:
A method, circuit and drive for improving clock recovery in clock/data signals are provided. A timing reference is provided to a locking loop circuit, such as a PLL. The timing reference is updated based on an expectation of a frequency of a clock being recovered. A system clock tracked to each clock being recovered is outputted. A current frequency of each system clock is approximated, and the expectation updated based on the approximated current frequency of one or more of the system clocks. If the data stream includes data separated into a series of blocks, the update may be made after an end of a block and before a beginning of a succeeding block. The approximation may be made periodically and/or numerous times for each block.

Comparing Prioritizing Memory For String Searching In A Data Compression System

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US Patent:
56027648, Feb 11, 1997
Filed:
Dec 22, 1993
Appl. No.:
8/171705
Inventors:
Bijan Eskandari-Gharnin - Littleton CO
Galen G. Kerber - Northglenn CO
Assignee:
Storage Technology Corporation - Louisville CO
International Classification:
G06F 700
US Classification:
36471509
Abstract:
A method and apparatus that allows very fast string searches, wherein a new type of data structure called a Comparing and Prioritizing (CAP) Memory is utilized. The CAP memory allows data stored therein to be string searched at high speeds. That is, the CAP memory provides the ability to sequentially determine one or more locations of strings that exist in its data memory that are identical to a string in an incoming data stream. In a preferred embodiment, the output of the CAP memory is used for data compression.
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Galen G Kerber from Lafayette, CO, age ~62 Get Report