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Web C Chang

from Yorba Linda, CA
Age ~73
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Also known as:
Web Lubov Chang, Web Dee Chang, Web W Chang, Webb C Chang, G Chang, Chang Web, N Chang, Chung Chang G, Chang Webb, Chang G
Related to:
Joseph M Chang, 54Albert Chang, 46Wei Ju, 48Deborah Wang, 63Sun Y Hong, 54
Connected to:
Abilio Chang, 68Adrienne M Chang, 47Ah R Chang, 49Aki Chang, 76Akiko O Chang, 42Alfonso Chang, 81Alfredo J Chang, 41Amore G Chang, 95Amos C Chang, 67Amy Chang, 38

Web Chang Phones & Addresses

  • Yorba Linda, CA
  • 571 Holthouse Ter, Sunnyvale, CA 94087
  • 3704 Monte Sereno Ter, Fremont, CA 94539 (510) 714-7399 (510) 226-9445 (510) 445-0887
  • 44220 Arapaho Ave, Fremont, CA 94539 (510) 226-9008
  • Buffalo, NY
  • Berkeley, CA
  • Santa Clara, CA

Business Records

Name / Title
Company / Classification
Phones & Addresses
Web Chang
President
AITON TECHNOLOGY, INC
PO Box 35523, Los Gatos, CA 95030
Web Chang
President
JAS-MAL INTERNATIONAL
1459 High St, Santa Cruz, CA 95060
Web Chang
President
UNITED MICROMACHINING CORPORATION
1557A Ctr Pointe Dr, Milpitas, CA 95035
1557 Ctr Pointe Dr, Milpitas, CA 95035
Web Chang
President
ICT, INC
Semiconductors and Related Dev
2123 Ringwood Ave, San Jose, CA 95131
(408) 434-0678, (408) 434-0688

Publications

Us Patents

Application Specific Field Programmable Gate Array

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US Patent:
56873255, Nov 11, 1997
Filed:
Apr 19, 1996
Appl. No.:
8/634728
Inventors:
Web Chang - Fremont CA
International Classification:
G06F 1531
US Classification:
395284
Abstract:
An application specific field programmable gate array ("ASFPGA") includes at least two fixed functional units in a single IC chip. Depending upon a specific application for the ASFPGA, the fixed functional units may include one or more bus interfaces, event timers, an interrupt controller, a Direct Memory Access ("DMA") controller, system timers, a real-time clock, a Random Access Memory ("RAM"), a clock synthesizer, a RAM Digital-to-Analog Converter ("DAC"), a display interface, a register file, a compressed image encoder/decoder ("CODEC"), or similar functional units. The ASFPGA also includes a general purpose field programmable gate array ("FPGA"). The FPGA is configurable to effect a specific digital logic circuit interconnection between fixed functional units. After the FPGA has been configured, the fixed functional units together with the FPGA perform all the functions specified for a particular ASIC design.

Embedded Configurable Logic Asic

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US Patent:
62600877, Jul 10, 2001
Filed:
Mar 3, 1999
Appl. No.:
9/261244
Inventors:
Web Chang - Fremont CA
International Classification:
G06F 1300
US Classification:
710100
Abstract:
An Application Specific Integrated Circuit ("ASIC") (10, 30 and 40), which includes at least one hardware, non-programmable functional block (12, 14, 16, 18, 22, 32, 44, 46 and 48), also includes a programmable logic block ("PLB") (26). The PLB (26) is electrically programmable for performing at least one function that complements a function performed using the hardware, non-programmable functional block (12, 14, 16, 18, 22, 32, 44, 46 and 48). The presence of the PLB (26) in the ASIC providing system builders with an opportunity to readily differentiate products within their respective product lines by adding particular functions to the ASIC, and to also functionally differentiate among various products offered by competing system builders.
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Web C Chang from Yorba Linda, CA, age ~73 Get Report