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Freeman S Zhong

from San Jose, CA
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Also known as:
Roger Chung, Suijun F Zhong
Connected to:
Chuwen Zhong, 35Diyang Zhong, 38Jacinda W Zhong, 34Jason Zhong, 32Jesse J Zhong, 41Jianqiang Q Zhong, 58Lei L Zhong, 60Longgui Zhong, 59Lucy Zhong, 32Paul L Zhong, 36

Freeman Zhong Phones & Addresses

  • San Jose, CA
  • Albany, CA
  • Santa Clara, CA
  • 3995 Will Rogers Dr, San Jose, CA 95117

Work

Company: Lsi corporation Position: Senior design manager at lsi corporation

Industries

Semiconductors

Resumes

Resumes

Freeman Zhong Photo 1

Senior Design Manager At Lsi Corporation

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Location:
1320 Ridder Park Dr, San Jose, CA 95131
Industry:
Semiconductors
Work:
Lsi Corporation
Senior Design Manager at Lsi Corporation

Publications

Us Patents

Duty Cycle Counting Phase Calibration Scheme Of An Input/Output (I/O) Interface

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US Patent:
7688928, Mar 30, 2010
Filed:
Sep 5, 2006
Appl. No.:
11/516382
Inventors:
Cathy Ye Lin - San Jose CA, US
Freeman Zhong - San Ramon CA, US
Catherine Chow - San Jose CA, US
Yi Zeng - Fremont CA, US
Ryan Park - San Jose CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H03D 3/24
US Classification:
375376
Abstract:
In one embodiment a control unit of a communication system exchanging a multiple-phase time-interleaved data includes a first Phase-Locked Loop (PLL) to generate a set of un-calibrated multiple-phase signals of a first-clock; a second-PLL, a pulse generator, a pulse-width measurement unit and a phase calibration engine to evaluate adjustments required in a temporal location of a logically critical voltage transition edge in each signal in the un-calibrated set; and a phase adjustment unit to adjust the temporal location of the logically critical voltage transition edge in each signal in the un-calibrated set to generate a set of calibrated multiple-phase signals of the first-clock such that each signal in the calibrated set includes the logically critical voltage transition edge which is time skewed in a predetermined amount from the logically critical voltage transition edge in other signals in the same set within a predetermined accuracy.

System For Automatic Bandwidth Control Of Equalizer Adaptation Loops

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US Patent:
7813415, Oct 12, 2010
Filed:
Jun 11, 2007
Appl. No.:
11/760844
Inventors:
Ephrem C. Wu - San Mateo CA, US
Ye Liu - San Jose CA, US
Freeman V. Zhong - San Ramon CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H04B 1/38
US Classification:
375219, 375229, 375230, 375231, 375232, 375233, 375234
Abstract:
A method to reduce peak power consumption during adaptation for an integrated circuit (IC) with multiple serial link transceivers including the steps of (A) inactivating equalizer adaptation loops until a triggering event occurs, (B) when the triggering event occurs, determining whether the triggering event is a minor change or a major change, (C) when the triggering event is a minor change, spreading out activation of adaptation loops in time, and (D) when the triggering event is a major change, simultaneously activating all adaptation loops.

Hybrid Bump Capacitor

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US Patent:
7825522, Nov 2, 2010
Filed:
Apr 27, 2007
Appl. No.:
11/741195
Inventors:
Yikui (Jen) Dong - Cupertino CA, US
Steven L. Howard - Fort Collins CO, US
Freeman Y. Zhong - San Ramon CA, US
David S. Lowrie - San Jose CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H01L 23/48
H01L 27/108
US Classification:
257778, 257306, 257738
Abstract:
A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding and (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer.

Low Power Decision Feedback Equalization (Dfe) Through Applying Dfe Data To Input Data In A Data Latch

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US Patent:
7869498, Jan 11, 2011
Filed:
Feb 21, 2007
Appl. No.:
11/709568
Inventors:
Yi Zeng - Fremont CA, US
Freeman Zhong - San Ramon CA, US
Peter Windler - Fort Collins CO, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H03H 7/40
US Classification:
375233, 375229, 375230, 375231, 375232
Abstract:
Low power decision feedback equalization (DFE) through applying DFE data to input data in a data latch is disclosed. In one embodiment, a decision feedback equalization (DFE) system to remove a post cursor intersymbol interference (ISI) through feeding back previous data scaled with adaptive weights to the DFE system, with each slice of the DFE system may include a first set of decision feedback digital to analog converters (DACs) to generate a first DFE data obtained through the feeding back the previous data scaled with the adaptive weights and a first data latch to generate an output data of the each slice through applying the first DFE data to an input data of the each slice in the first data latch to remove a first delay caused by performing the applying the first DFE data to the input data of the each slice outside of the first data latch.

Self-Calibrated Wide Range Lc Tank Voltage-Controlled Oscillator (Vco) System With Expanded Frequency Tuning Range And Method For Providing Same

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US Patent:
7940140, May 10, 2011
Filed:
Jun 3, 2008
Appl. No.:
12/156607
Inventors:
Yi Zeng - Fremont CA, US
Freeman Zhong - San Ramon CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H03L 7/099
H03L 1/00
H03B 5/08
US Classification:
331179, 331 36 C, 331 44, 331 49, 331167, 331186
Abstract:
The present invention is a self-calibrating, dual-band, wide range LC tank Voltage Controlled Oscillator (VCO) system. The system may include a first Voltage-Controlled Oscillator (VCO) and a second Voltage-Controlled Oscillator (VCO). The system may further include a calibration engine. The calibration engine may be configured for being connectable to at least one of the first VCO or the second VCO. The calibration engine may further be configured for automatically establishing/providing a VCO fix capacitor band code setting and a gear control setting for selectively activating or inactivating the first VCO and/or the second VCO. The calibration engine may be further configured for automatically comparing a VCO control voltage of the system to an allowable control voltage range for the system and may be further configured for automatically adjusting the VCO fix capacitor band code setting and/or the gear control setting when the VCO control voltage falls outside of the allowable control voltage range.

Ac Coupling Circuit Integrated With Receiver With Hybrid Stable Common-Mode Voltage Generation And Baseline Wander Compensation

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US Patent:
7961817, Jun 14, 2011
Filed:
Dec 6, 2006
Appl. No.:
11/634671
Inventors:
Yikui (Jen) Dong - Cupertino CA, US
Cathy Ye Liu - San Jose CA, US
Freeman Yingquan Zhong - San Ramon CA, US
Shao Ming Hsu - San Jose CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H04L 25/06
H04L 25/10
US Classification:
375317, 375233, 375319, 333 28 R, 327307
Abstract:
In a receiver, an AC-coupling solution uses a fully integrated circuit for simultaneously providing both baseline wander compensation and common-mode voltage generation. Usefully, an integrated capacitor is placed between the receiver input pin and the input buffer, and a high resistive impedance element is connected to the internal high-speed data node after the capacitor. An on-chip voltage generation and correction circuit is connected to the other side of the impedance element to generate a common-mode voltage, and to provide dynamic, fine adjustment for the received data voltage level. The voltage correction circuit is controlled by the feedback of data detected by the clock and data recovery unit (CDRU) of the receiver. The feedback data passes through a weighting element, wherein the amount of feedback gain is adjustable to provide a summing weight and thereby achieve a desired BLW compensation. Register bits are used to control an on-chip reference voltage generator that consists of a resistor ladder to generate the reference voltage.

Re-Adaption Of Equalizer Parameter To Center A Sample Point In A Baud-Rate Clock And Data Recovery Receiver

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US Patent:
8102910, Jan 24, 2012
Filed:
Sep 29, 2008
Appl. No.:
12/240046
Inventors:
Freeman Y. Zhong - San Ramon CA, US
Amaresh V. Malipatil - Milpitas CA, US
Yikui Dong - Cupertino CA, US
Venkata Naga Jyothi Madhavapeddy - Sunnyvale CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H04L 27/01
US Classification:
375233, 375229, 375230, 375231, 375232, 375234, 375348
Abstract:
An apparatus generally having a first circuit and a second circuit. The first circuit may be configured to (i) generate an equalizer parameter in response to an input signal, the equalizer parameter causing a cancellation of post-cursor inter-symbol interference from a plurality of symbols in the input signal and (ii) generate an output signal in response to both the input signal and the equalizer parameter. The second circuit may be configured to (i) generate a target parameter signal in response to the input signal, the target parameter signal representing a mean value of a plurality of sample points of the symbols and (ii) generate a control signal in response to the target parameter signal, the control signal causing a reduction of the equalizer parameter, the reduction causing a decrease in the cancellation of the post-cursor inter-symbol interference from the symbols, wherein the apparatus does not cancel pre-cursor inter-symbol interference.

System For An Adaptive Floating Tap Decision Feedback Equalizer

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US Patent:
8121183, Feb 21, 2012
Filed:
Jul 13, 2007
Appl. No.:
11/777337
Inventors:
Lizhi Zhong - Sunnyvale CA, US
Ye Liu - San Jose CA, US
Catherine Yuk-fun Chow - San Jose CA, US
Ryan Jungsuk Park - San Jose CA, US
Freeman V. Zhong - San Ramon CA, US
Amaresh V. Malipatil - Milpitas CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H03K 5/159
US Classification:
375230, 375233, 375229, 375234
Abstract:
A method for adaptive selection of floating taps in a decision feedback equalizer including the steps of (A) determining values for a predefined metric for tap positions within a range covered by a decision feedback equalizer (DFE) and (B) setting one or more floating taps of the DFE to tap positions based upon the values of the predefined metric.
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Freeman S Zhong from San Jose, CA Get Report