Frank A Cassarino

41595343, Jun 26, 1979

Aug 4, 1977

5/821939

Edward F. Getson - Lynn MA
Frank V. Cassarino - Weston MA

Honeywell Information Systems Inc. - Waltham MA

G06F 1100

364200

A firmware/hardware method and system is provided for testing interface logic in a data processing system having a plurality of system units intercommunicating over a common electrical bus. Under firmware control, an incorrect parity is generated in a main memory address to be loaded into output registers of a system unit supplying information to the bus. A bus cycle request is issued by the system unit, and when the bus is made available the system unit acknowledges the memory address to initiate a transfer of data from the bus into the input registers of the system unit. Thereafter, the data in the output registers of the device may be compared with the data in the input registers to detect interface logic errors.

40004856, Dec 28, 1976

Jun 30, 1975

5/591904

George J. Barlow - Tewksbury MA
Frank V. Cassarino - Weston MA
John W. Conway - Waltham MA
David B. O'Keefe - Tyngsboro MA

Honeywell Information Systems, Inc. - Waltham MA

G06F 918

3401725

A central processing system which includes a plurality of units coupled over a common electrical bus for the transfer of information between any two units, includes one unit in which there is a shareable resource such as a memory for example. Apparatus is provided for any units to share such resource. Further apparatus is provided for enabling any of such units so sharing the resource to lock out any other unit which presents a specified control signal to the unit incorporating the resource.

39939812, Nov 23, 1976

Jun 30, 1975

5/591964

Frank V. Cassarino - Weston MA
George J. Barlow - Tewksbury MA
George J. Bekampis - Sudbury MA
John W. Conway - Waltham MA
Richard A. Lemay - Bolton MA
David B. O'Keefe - Tyngsboro MA
Douglas L. Riikonen - Westford MA
William E. Woods - Natwick MA

Honeywell Information Systems, Inc. - Waltham MA

G06F 304
G06F 1300

3401725

In a data processing system having a plurality of units coupled for the transfer of information therebetween over a common electrical bus during asynchronously generated information bus transfer cycles, the units are coupled in a priority network and depending upon their respective priority may gain access to the bus before a lower priority unit is so enabled. Each one of the units includes apparatus for responding to a request for the transfer of information from another unit by providing any one of up to three signal responses including a positive acknowledge signal indicating an immediate response, a negative acknowledge signal indicating that the unit will most likely be busy for a relatively extended period of time and a quasi-negative response indicating that the unit will probably be ready during the next asynchronously generated bus transfer cycle.

40428320, Aug 16, 1977

Dec 29, 1975

5/644653

Frank V. Cassarino - Weston MA
George J. Barlow - Tewksbury MA

Honeywell Information Systems Inc. - Waltham MA

H02J 1300

307149

A plurality of logic boards coupled together over a common electrical bus by use of a plurality of connectors, at least one per board, which includes at least one pair of terminals for coupling an interlock signal wire which is daisy chained through each of such boards and connectors. By providing a known signal state on the interlock signal wire at one end of the bus, an improper connection or an error condition in one of the logic boards will be indicated by a sensor, which may be included at the last logic board, if the known signal state is not received at the sensor.

39978966, Dec 14, 1976

Jun 30, 1975

5/591965

Frank V. Cassarino - Weston MA
George J. Bekampis - Sudbury MA
John W. Conway - Waltham MA
Richard A. Lemay - Bolton MA

Honeywell Information Systems, Inc. - Waltham MA

G06F 1300

3401725

In a data processing system which includes a common bus to which a plurality of units are connected for the transfer of information, information may be transferred by the highest priority requesting unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a split bus cycle operation in which the master unit requesting information from the slave unit during a first bus transfer cycle may receive such information from the slave unit during a later slave generated bus transfer cycle. Means are provided for enabling any other units to communicate over the common bus during the time between the first cycle and such later cycle during which the slave unit responds, thereby enabling at least two pairs of units to communicate with each other respectively in an interleaved manner.

40385370, Jul 26, 1977

Dec 22, 1975

5/643453

Frank V. Cassarino - Weston MA
Thomas O. Holtey - Newton Lower Falls MA
Douglas L. Riikonen - Westford MA

Honeywell Information Systems, Inc. - Waltham MA

G06F 1110

235153AM

A memory having a plurality of word locations, each having a bit location, includes a parity word in one of the word locations. Bit selector means selects a column of bits made up of like positioned bits in each of the word locations. All bits in a column are added together to indicate whether there is a successful parity check. Each such column is successively checked thereby verifying the integrity of the stored information on a column basis.