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Foroozan Sarah Koushan

from San Jose, CA
Age ~50
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Also known as:
Foroozan S Koushan, Foroozan Trus Koushan, Foroozan K Taheri, Oushan O Foroozan, Faroozan Koushan, Foroozan N
Phone and address:
1234 Linder Hill Ln, San Jose, CA 95120
Related to:
Kevin E Alkhas, 27Jacobs Nanet Alkh, 58Irene Yeganegi, 94Farine F Yeganegi, 57Farima Yeganegi, 64Ramtin N Taheri, 67Ferial Y Yeganegi, 63
Connected to:
Kenneth S Koushel, 68Ali Kousheshian, 80Kavitha N Koushik, 48Paul Kousis, 53Achilles C Kouskoutis, 65Katie E Kousma, 40Rima A Koussa, 57Youssef Koussa, 59Wendy L Koussis, 70George A Koussoglou, 52

Foroozan Koushan Phones & Addresses

  • 1234 Linder Hill Ln, San Jose, CA 95120
  • 6847 Burnside Dr, San Jose, CA 95120 (408) 323-5511
  • 24150 Big Basin Way, Saratoga, CA 95070 (408) 868-9286 (408) 868-9287
  • Mountain View, CA
  • Santa Clara, CA
  • 6713 Bret Harte Dr, San Jose, CA 95120 (408) 323-5511

Education

Degree: High school graduate or higher

Resumes

Resumes

Foroozan Koushan Photo 1

Device Manager; R&D Group At Adesto Technologies

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Position:
Device Manager; R&D Group at Adesto Technologies
Location:
San Francisco Bay Area
Industry:
Electrical/Electronic Manufacturing
Work:
Adesto Technologies - Sunnyvale, CA since Mar 2012
Device Manager; R&D Group
Adesto Technologies - Sunnyvale, CA Nov 2007 - Mar 2012
MTS; R&D Group
Monolithic Power Systems May 2005 - Oct 2006
Device Engineer
Micrel Semiconductor 2002 - 2005
Device and Process Development Engineer
Education:
San Jose State University 2000 - 2003
MS, Electrical Engineering San Jose State University 1997 - 2000
BS, Physics - Solid States
Foroozan Koushan Photo 2

Senior Member Of 3D Nand Adt

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Location:
San Jose, CA
Industry:
Semiconductors
Work:
Micron Technology
Senior Member of 3D Nand Adt
Adesto Technologies Nov 2007 - Mar 2018
Mts Device Engineer
Monolithic Power Systems, Inc. Sep 2005 - Sep 2006
Device Engineer
Micrel May 2002 - May 2005
Device and Process Development Engineer
Education:
University of California, Santa Cruz 2017 - 2020
Doctorates, Doctor of Philosophy, Philosophy San Jose State University 2000 - 2003
Masters, Electronics Engineering San Jose State University 1997 - 2000
Bachelors, Physics
Skills:
Semiconductors
Product Development
Testing
Electronics
Product Marketing
Start Ups
Ic
Debugging
Mixed Signal Ic Design
Cmos
Failure Analysis
Semiconductor Industry
Characterization
Languages:
English
Farsi

Publications

Us Patents

Resistive Switching Devices Having Alloyed Electrodes And Methods Of Formation Thereof

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US Patent:
20130062587, Mar 14, 2013
Filed:
Jul 25, 2012
Appl. No.:
13/558296
Inventors:
Wei Ti Lee - San Jose CA, US
Chakravarthy Gopalan - Santa Clara CA, US
Yi Ma - Santa Clara CA, US
Jeffrey Shields - Sunnyvale CA, US
Philippe Blanchard - Moigny sur Ecole, FR
John Ross Jameson - Burlingame CA, US
Foroozan Sarah Koushan - San Jose CA, US
Janet Wang - Los Altos CA, US
Mark Kellam - Siler City NC, US
Assignee:
ADESTO TECHNOLOGIES CORP. - Sunnyvale CA
International Classification:
H01L 47/00
H01L 21/02
US Classification:
257 4, 438382, 257E47001, 257E21004
Abstract:
In accordance with an embodiment of the present invention, a resistive switching device comprises a bottom electrode, a switching layer disposed over the bottom electrode, and a top electrode disposed over the switching layer. The top electrode comprises an alloy of a memory metal and an alloying element. The top electrode provides a source of the memory metal. The memory metal is configured to change a state of the switching layer.

Memory Devices And Methods Having Adaptable Read Threshold Levels

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US Patent:
20130258753, Oct 3, 2013
Filed:
Mar 26, 2013
Appl. No.:
13/851011
Inventors:
Foroozan Sarah Koushan - San Jose CA, US
Derric Jawaher Herman Lewis - Sunnyvale CA, US
Assignee:
Adesto Technologies Corporation - Sunnyvale CA
International Classification:
G11C 13/00
US Classification:
365148
Abstract:
A method can include determining at least one use characteristic for the memory cells comprising a solid electrolyte, the use characteristic corresponding to a number of times the memory cells have been programmed to at least one impedance level; and adjusting a read threshold level for the memory cells based on at least the use characteristic, the read threshold level determining data values stored in the memory cells in a read operation.

Resistive Devices And Methods Of Operation Thereof

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US Patent:
20130301337, Nov 14, 2013
Filed:
May 11, 2012
Appl. No.:
13/470030
Inventors:
Deepak Kamalanathan - Santa Clara CA, US
Foroozan Sarah Koushan - San Jose CA, US
Juan Pablo Saenz Echeverry - Mountain View CA, US
John Dinh - Dublin CA, US
Shane C. Hollmer - Grass Valley CA, US
Michael Kozicki - Phoenix AZ, US
Assignee:
Axon Technologies Corporation - Scottsdale AZ
Adesto Technologies Corporation - Sunnyvale CA
International Classification:
G11C 11/00
US Classification:
365148
Abstract:
In one embodiment, a method of operating a resistive switching device includes applying a signal comprising a pulse on a first terminal of a two terminal resistive switching device having the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period. The first time period is at least 0.1 times a total time period of the pulse.

Resistive Devices And Methods Of Operation Thereof

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US Patent:
20140003125, Jan 2, 2014
Filed:
Sep 11, 2012
Appl. No.:
13/610690
Inventors:
Foroozan Sarah Koushan - San Jose CA, US
Michael A. Van Buskirk - Saratoga CA, US
Assignee:
ADESTO TECHNOLOGIES CORPORATION - Sunnyvale CA
International Classification:
G11C 11/00
US Classification:
365148
Abstract:
In accordance with an embodiment of the present invention, a method of operating a resistive switching device includes applying a signal including a pulse on a first access terminal of an access device having the first access terminal and a second access terminal. The second access terminal is coupled to a first terminal of a two terminal resistive switching device. The resistive switching device has the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period, a second ramp from the second voltage to a third voltage over a second time period, and a third ramp from the third voltage to a fourth voltage over a third time period. The second ramp and the third ramp have an opposite slope to the first ramp. The sum of the first time period and the second time period is less than the third time period.

Variable Impedance Memory Element Structures, Methods Of Manufacture, And Memory Devices Containing The Same

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US Patent:
8624219, Jan 7, 2014
Filed:
Apr 12, 2012
Appl. No.:
13/445389
Inventors:
John Ross Jameson - Burlingame CA, US
Antonio R. Gallo - San Mateo CA, US
Foroozan Sarah Koushan - San Jose CA, US
Michael A. Van Buskirk - Saratoga CA, US
Assignee:
Adesto Technologies Corporation - Sunnyvale CA
International Classification:
H01L 47/00
US Classification:
257 4, 257 3, 257 42, 257 43, 257E45002, 257E45003, 438 85, 438104
Abstract:
A memory device can include at least one cathode formed in first opening of a first insulating layer; at least one anode formed in a second opening of second insulating layer, the second insulating layer being a different vertical layer than the first insulating layer; and a memory layer comprising an ion conductor layer extending laterally between the at least one anode and cathode on the first insulating layer, the ion conductor layer having a thickness in the vertical direction less than a depth of the first opening.

Memory Devices Including Heaters

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US Patent:
20220351755, Nov 3, 2022
Filed:
Jul 18, 2022
Appl. No.:
17/866903
Inventors:
- BOISE ID, US
Foroozan Koushan - Fremont CA, US
Jayasree Nayar - Pleasanton CA, US
Ji-Hye Gale Shin - Palo Alto CA, US
Assignee:
MICRON TECHNOLOGY, INC. - BOISE ID
International Classification:
G11C 5/02
H01L 27/11524
H01L 27/1157
H01L 27/11529
Abstract:
Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.

Memory Devices Including Heaters

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US Patent:
20220189512, Jun 16, 2022
Filed:
Feb 22, 2021
Appl. No.:
17/181125
Inventors:
- BOISE ID, US
Foroozan Koushan - Fremont CA, US
Jayasree Nayar - Pleasanton CA, US
Ji-Hye Gale Shin - Palo Alto CA, US
Assignee:
MICRON TECHNOLOGY, INC. - BOISE ID
International Classification:
G11C 5/02
H01L 27/11524
H01L 27/11529
H01L 27/1157
Abstract:
Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.

Managing Pre-Programming Of A Memory Device For A Reflow Process

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US Patent:
20210343346, Nov 4, 2021
Filed:
Jul 12, 2021
Appl. No.:
17/373701
Inventors:
- Boise ID, US
Foroozan S. Koushan - San Jose CA, US
Tomoko Iwasaki - San Jose CA, US
Jayasree Nayar - San Jose CA, US
International Classification:
G11C 16/12
G11C 16/34
G06F 3/06
Abstract:
A system includes a memory device and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations that include determining a verify reference voltage associated with a logic state of a memory cell of the memory device, the verify reference voltage defining a target voltage level of a threshold voltage associated with the logic state; determining an amount of voltage compensation based on a thermal profile associated with a heat to be applied to the memory device, the thermal profile comprising a temperature associated with the heat and a period of time the heat is to be applied to the memory device; and updating the verify reference voltage using the amount of voltage compensation for an expected shift in the threshold voltage of the memory cell after the heat is applied to the memory device.
Control profile
Foroozan Sarah Koushan from San Jose, CA, age ~50 Get Report