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Faris T Modawar

from Georgetown, TX
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Also known as:
Faris Terrie Modawar, Faris A Modawar
Phone and address:
314 Fawnridge St, Georgetown, TX 78628
(512) 259-5780
Connected to:
Lauren K Modawell, 35Michelle R Moday, 55Patrick Moday, 49Lyle A Moddelmog, 85Jason A Modderman, 39Jon M Modderman, 60Paul T Modderman, 73Stephanie L Moddie, 37Dawn M Mode, 57John M Modeck, 63

Faris Modawar Phones & Addresses

  • 314 Fawnridge St, Georgetown, TX 78628 (512) 259-5780
  • 346 Fawnridge St, Georgetown, TX 78628 (512) 259-5780
  • Orem, UT
  • Colorado Springs, CO
  • 314 Fawnridge St, Georgetown, TX 78628 (512) 470-3765

Skills

Spc • Characterization • Microsoft Office • Design of Experiments • Manufacturing • Microsoft Excel • Optics • Semiconductors • Testing • R&D • Lean Manufacturing • Process Engineering

Emails

t***[email protected]

Resumes

Resumes

Faris Modawar Photo 1

Faris Modawar

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Skills:
Spc
Characterization
Microsoft Office
Design of Experiments
Manufacturing
Microsoft Excel
Optics
Semiconductors
Testing
R&D
Lean Manufacturing
Process Engineering
Faris Modawar Photo 2

Faris Modawar Orem, UT

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Work:
MOXTEK

2012 to 2000
Statistical Process Control and Defect Reduction Coordinator
BANDGAP ENGINEERING
Woburn, MA
2008 to 2012
Senior Research and Development Engineer
Retail Store

2003 to 2007
Owner/Manager
MOTOROLA
Austin, TX
1996 to 2003
Development Engineer of Advance Product Reticles
KLA INSTRUMENTS
Santa Clara, CA
1988 to 1995
Central Region Senior Defect Reduction Application Engineer
Education:
John Jay College of Criminal Justice
New York, NY
BS in Science and Chemistry
George Washington University
Washington, DC
Faris Modawar Photo 3

Faris Modawar Georgetown, TX

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Work:
BANDGAP ENGINEERING

2008 to 2000
Senior Research and Development Engineer
Mac Haik Dodge
Georgetown, TX
2007 to 2008
Auto Salesman
Owner/Manager of a Retail Store
2003 to 2007
MOTOROLA
Austin, TX
1996 to 2003
Development Engineer of Advance Product Reticles
Education:
John Jay College of Criminal Justice
New York, NY
BS in Science and Chemistry
George Washington University Washington DC
George, WA

Publications

Us Patents

Process For Fabricating Nanowire Arrays

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US Patent:
8143143, Mar 27, 2012
Filed:
Apr 14, 2009
Appl. No.:
12/423623
Inventors:
Brent A. Buchine - Watertown MA, US
Faris Modawar - Georgetown TX, US
Marcie R. Black - Lincoln MA, US
International Classification:
H01L 21/20
US Classification:
438478, 257E21219, 977762
Abstract:
A process is provided for etching a silicon-containing substrate to form nanowire arrays. In this process, one deposits nanoparticles and a metal film onto the substrate in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. One submerges the metallized substrate into an etchant aqueous solution comprising HF and an oxidizing agent. In this way arrays of nanowires with controlled diameter and length are produced.

Nanostructured Devices

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US Patent:
8450599, May 28, 2013
Filed:
Nov 16, 2009
Appl. No.:
12/619092
Inventors:
Brent A. Buchine - Watertown MA, US
Faris Modawar - Georgetown TX, US
Marcie R. Black - Lincoln MA, US
Assignee:
Bandgap Engineering, Inc. - Woburn MA
International Classification:
H01L 31/00
H01L 21/00
US Classification:
136255, 136256, 136261, 438 57, 977948
Abstract:
A photovoltaic device is provided. It comprises at least two electrical contacts, p type dopants and n type dopants. It also comprises a bulk region and nanowires in an aligned array which contact the bulk region. All nanowires in the array have one predominant type of dopant, n or p, and at least a portion of the bulk region also comprises that predominant type of dopant. The portion of the bulk region comprising the predominant type of dopant typically contacts the nanowire array. The photovoltaic devices' p-n junction would then be found in the bulk region. The photovoltaic devices would commonly comprise silicon.

Process For Structuring Silicon

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US Patent:
20100092888, Apr 15, 2010
Filed:
Oct 9, 2009
Appl. No.:
12/576490
Inventors:
Brent A. Buchine - Watertown MA, US
Faris Modawar - Georgetown TX, US
Marcie R. Black - Lincoln MA, US
International Classification:
G03F 7/20
B32B 3/10
B32B 15/00
C23F 1/00
H01L 33/00
H01L 31/0216
US Classification:
430296, 428156, 428173, 216 95, 216 49, 216 40, 438 42, 216 24, 216 17, 438 98, 257E33066, 257E31119, 977762
Abstract:
A process for etching a silicon-containing substrate to form structures is provided. In the process, a metal is deposited and patterned onto a silicon-containing substrate (commonly one with a resistivity above 1-10 ohm-cm) in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. The metallized substrate is submerged into an etchant aqueous solution comprising about 4 to about 49 weight percent HF and an oxidizing agent such as about 0.5 to about 30 weight percent HO, thus producing a metallized substrate with one or more trenches. A second silicon etch is optionally employed to remove nanowires inside the one or more trenches.

Silicon Nanowire Arrays On An Organic Conductor

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US Patent:
20110024169, Feb 3, 2011
Filed:
Jul 28, 2010
Appl. No.:
12/845557
Inventors:
Brent A. Buchine - Watertown MA, US
Jeff Miller - Cambridge MA, US
Marcie R. Black - Lincoln MA, US
Faris Modawar - Georgetown TX, US
International Classification:
H05K 1/00
C23F 1/24
B82Y 30/00
US Classification:
174258, 174250, 216 13, 977762, 977932
Abstract:
In an aspect of the invention, a process to make a nanowire array is provided. In the process, silicon is deposited onto a conductive substrate comprising an organic material and optionally a conductive layer, thus forming a silicon-containing layer. Nanoparticles are deposited on top of the silicon-containing layer. Metal is deposited on top of the nanoparticles and silicon in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. The metallized substrate is contacted with an etchant aqueous solution comprising about 2 to about 49 weight percent HF and an oxidizing agent.

Nanowire Device With Alumina Passivation Layer And Methods Of Making Same

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US Patent:
20120153250, Jun 21, 2012
Filed:
Jan 18, 2012
Appl. No.:
13/353087
Inventors:
Faris Modawar - Georgetown TX, US
Marcie R. Black - Lincoln MA, US
Brian Murphy - Revere MA, US
Jeff Miller - Brookline MA, US
Mike Jura - Boston MA, US
Assignee:
Bandgap Engineering, Inc. - Woburn MA
International Classification:
H01L 31/0352
US Classification:
257 9, 438 57, 257E31032
Abstract:
In one aspect, the present disclosure relates to a device including a silicon substrate, wherein at least a portion of the substrate surface can be a silicon nanowire array; and a layer of alumina covering the silicon nanowire array. In some embodiments, the device can be a solar cell. In some embodiments, the device can be a p-n junction. In some embodiments, the p-n junction can be located below the bottom surface the nanowire array.

Selective Emitter Nanowire Array And Methods Of Making Same

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US Patent:
20120153251, Jun 21, 2012
Filed:
Jan 18, 2012
Appl. No.:
13/353091
Inventors:
Faris Modawar - Georgetown TX, US
Marcie R. Black - Lincoln MA, US
Brian Murphy - Revere MA, US
Jeff Miller - Brookline MA, US
Mike Jura - Boston MA, US
Assignee:
Bandgap Engineering, Inc. - Wobum MA
International Classification:
H01L 29/06
H01L 21/20
B82Y 99/00
B82Y 40/00
US Classification:
257 9, 438478, 257E2109, 257E29024, 977762, 977890
Abstract:
Another aspect of the present disclosure relates to a device including a substrate, having a top surface and a bottom surface; an array of nanowires having a base and a top surface, the base contacting the top surface of the substrate; a contacting structure including the same material as the substrate having a non-nanostructured surface of a dimension suitable for forming an electrical contact, located on the same side of the substrate as the array of silicon nanowires; wherein the contacting structure is doped with a greater impurity concentration than the nanowire array, thereby forming a selective emitter.

Method Of Electrically Contacting Nanowire Arrays

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US Patent:
20120181502, Jul 19, 2012
Filed:
Jan 18, 2012
Appl. No.:
13/353080
Inventors:
Faris Modawar - Georgetown TX, US
Marcie R. Black - Lincoln MA, US
Brian Murphy - Revere MA, US
Jeff Miller - Brookline MA, US
Mike Jura - Boston MA, US
Assignee:
Bandgap Engineering, Inc. - Woburn MA
International Classification:
H01L 29/06
H01L 21/20
B82Y 40/00
B82Y 99/00
US Classification:
257 9, 438478, 257E29024, 257E2109, 977890, 977762
Abstract:
In one aspect, the present disclosure relates to a device including a substrate, having a top surface and a bottom surface; an array of nanowires having a base and a top surface, the base contacting the top surface of the substrate; a contacting structure having a non-nanostructured surface, having a top surface and a bottom surface, located on the same side of the substrate as the array of silicon nanowires; and an electrical contact in contact with the top surface of the contacting structure. In some embodiments, the device includes an aluminum oxide passivation layer over the array of nanowires. In some embodiments, the layer of aluminum oxide is deposited via atomic layer deposition.

Process For Fabricating Nanowire Arrays

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US Patent:
20120301785, Nov 29, 2012
Filed:
Nov 28, 2011
Appl. No.:
13/305649
Inventors:
Brent A. Buchine - Watertown MA, US
Faris Modawar - Georgetown TX, US
Marcie R. Black - Lincoln MA, US
Assignee:
BANDGAP ENGINEERING INC. - Woburn MA
International Classification:
H01M 4/134
H01M 4/04
H01L 29/16
H01L 21/28
B82Y 40/00
B82Y 99/00
US Classification:
4292181, 257 9, 438686, 216 13, 257E29082, 977762, 257E21158, 977888
Abstract:
A process is provided for etching a silicon-containing substrate to form nanowire arrays. In this process, one deposits nanoparticles and a metal film onto the substrate in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. One submerges the metallized substrate into an etchant aqueous solution comprising HF and an oxidizing agent. In this way arrays of nanowires with controlled diameter and length are produced.
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Faris T Modawar from Georgetown, TX Get Report