Search

Eric A Sprangle

from Austin, TX
Age ~54
Get Report
Also known as:
Eric Eric Sprangle, Sabrina Sprangle, Eric A Prangle, Eric Sprange
Phone and address:
4205 Bennedict Ln, Austin, TX 78746
Related to:
Delores A Sprankel, 80Whitney Kiefer, 53Tim S HendrixsonGina SprankelMargaret R Freitas, 64Karen Billman, 68
Connected to:
Andrew T Sprankle, 44Danielle Sprankle, 31Martin W Sprankle, 67Mike C Sprankle, 45Ryan M Sprankle, 32Shawn A Sprankle, 35Tammy Sprankle, 55Trina L Sprankle, 54Alexandra N Sprano, 39Joseph R Spransy, 74

Eric Sprangle Phones & Addresses

  • 4205 Bennedict Ln, Austin, TX 78746
  • 4700 Golden Maize Dr, Austin, TX 78746
  • 10290 Arborcrest Way, Portland, OR 97225
  • 13456 Hawks Beard St, Portland, OR 97223
  • Tigard, OR
  • Sioux Falls, SD
  • Ann Arbor, MI

Work

Company: Nvidia Jan 2012 Position: Processor architect

Education

Degree: Master of Science, Masters School / High School: University of Michigan 1992 to 1995 Specialities: Engineering

Industries

Computer Hardware

Resumes

Resumes

Eric Sprangle Photo 1

Processor Architect

View page
Location:
Austin, TX
Industry:
Computer Hardware
Work:
Nvidia
Processor Architect
Education:
University of Michigan 1992 - 1995
Master of Science, Masters, Engineering Cornell University 1989 - 1993
Bachelors, Bachelor of Science, Engineering

Publications

Us Patents

Method And Apparatus To Control Memory Accesses

View page
US Patent:
6799257, Sep 28, 2004
Filed:
Feb 21, 2002
Appl. No.:
10/079967
Inventors:
Eric A. Sprangle - Portland OR
Onur Mutlu - Austin TX
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1200
US Classification:
711158
Abstract:
A method and apparatus for accessing memory comprising monitoring memory accesses from a hardware prefetcher and determining whether the memory accesses from the hardware prefetcher are used by an out-of-order core. A front side bus controller switches memory access modes from a minimize memory access latency mode to a maximize memory bus bandwidth mode if a percentage of the memory accesses generated by the hardware prefetcher are used by the out-of-order core.

Speculative Scheduling Of Instructions With Source Operand Validity Bit And Rescheduling Upon Carried Over Destination Operand Invalid Bit Detection

View page
US Patent:
6925550, Aug 2, 2005
Filed:
Jan 2, 2002
Appl. No.:
10/040223
Inventors:
Eric Sprangle - Portland OR, US
Michael J. Haertel - Portland OR, US
David J. Sager - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F009/38
US Classification:
712214, 712 23, 712217, 712218
Abstract:
A method and apparatus to execute data speculative instructions in a processor comprising at least one source register, each source register comprising a bit to indicate validity of data in the at least one source register. A data validity circuit coupled to the one or more source registers to determine the validity of the data in the source registers, and to indicate the validity of the data in a destination register based upon the validity bit in the at least one source register. The processor optionally comprising a checker unit to retire those instructions from the execution unit which write valid data to the destination register, and to re-schedules those instructions for execution which write invalid data to the destination register.

Method And Apparatus For Determining A Dynamic Random Access Memory Page Management Implementation

View page
US Patent:
7020762, Mar 28, 2006
Filed:
Dec 24, 2002
Appl. No.:
10/328576
Inventors:
Eric A. Sprangle - Portland OR, US
Anwar Q. Rohillah - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
US Classification:
711204, 711154, 711167
Abstract:
A system and method for a processor to determine a memory page management implementation used by a memory controller without necessarily having direct access to the circuits or registers of the memory controller is disclosed. In one embodiment, a matrix of counters correspond to potential page management implementations and numbers of pages per block. The counters may be incremented or decremented depending upon whether the corresponding page management implementations and numbers of pages predict a page boundary whenever a long access latency is observed. The counter with the largest value after a period of time may correspond to the actual page management implementation and number of pages per block.

Prefetching Data In A Computer System

View page
US Patent:
7032076, Apr 18, 2006
Filed:
Sep 16, 2002
Appl. No.:
10/244250
Inventors:
Eric A. Sprangle - Portland OR, US
Anwar Q. Rohillah - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
US Classification:
711137, 711213, 712205, 712207
Abstract:
A method and apparatus to detect and filter out redundant cache line addresses in a prefetch input queue, and to adjust the detector window size dynamically according to the number of detector entries in the queue for the cache-to-memory controller bus. Detectors correspond to cache line addresses that may represent cache misses in various levels of cache memory.

Prefetching Data In A Computer System

View page
US Patent:
7296140, Nov 13, 2007
Filed:
Jan 12, 2006
Appl. No.:
11/331658
Inventors:
Eric A. Sprangle - Portland OR, US
Anwar Q. Rohillah - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
US Classification:
711213, 711204, 712207
Abstract:
A method and apparatus to detect and filter out redundant cache line addresses in a prefetch input queue, and to adjust the detector window size dynamically according to the number of detector entries in the queue for the cache-to-memory controller bus. Detectors correspond to cache line addresses that may represent cache misses in various levels of cache memory.

Method And Apparatus For Prefetching Data To A Lower Level Cache Memory

View page
US Patent:
7383418, Jun 3, 2008
Filed:
Sep 1, 2004
Appl. No.:
10/933188
Inventors:
Kenneth J. Janik - Beaverton OR, US
K S Venkatraman - Hillsboro OR, US
Anwar Rohillah - Hillsboro OR, US
Eric Sprangle - Portland OR, US
Ronak Singhal - Portland OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
G06F 9/34
G06F 9/26
US Classification:
711216, 711137, 711117, 711118, 711119, 710 52
Abstract:
A prefetching scheme to detect when a load misses the lower level cache and hits the next level cache. Consequently, the prefetching scheme utilizes the previous information for the cache miss to the lower level cache and hit to the next higher level of cache memory that may result in initiating a sidedoor prefetch load for fetching the previous or next cache line into the lower level cache. In order to generate an address for the sidedoor prefetch, a history of cache access is maintained in a queue.

Method And Apparatus For Determining A Dynamic Random Access Memory Page Management Implementation

View page
US Patent:
7536530, May 19, 2009
Filed:
Dec 30, 2005
Appl. No.:
11/323598
Inventors:
Eric A. Sprangle - Portland OR, US
Anwar Q. Rohillah - Hillsboro OR, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/02
US Classification:
711204, 711103, 711104, 711105, 711154, 711157, 711159, 711205, 711206, 711209
Abstract:
A system and method for a processor to determine a memory page management implementation used by a memory controller without necessarily having direct access to the circuits or registers of the memory controller is disclosed. In one embodiment, a matrix of counters correspond to potential page management implementations and numbers of pages per block. The counters may be incremented or decremented depending upon whether the corresponding page management implementations and numbers of pages predict a page boundary whenever a long access latency is observed. The counter with the largest value after a period of time may correspond to the actual page management implementation and number of pages per block.

System And Method For Using A Mask Register To Track Progress Of Gathering Elements From Memory

View page
US Patent:
7984273, Jul 19, 2011
Filed:
Dec 31, 2007
Appl. No.:
11/967482
Inventors:
Eric Sprangle - Austin TX, US
Anwar Rohillah - Austin TX, US
Robert Cavin - San Francisco CA, US
Tom Forsyth - Kirkland WA, US
Michael Abrash - Kirkland WA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/312
US Classification:
712225, 712 4, 712 6
Abstract:
A system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.
Control profile
Eric A Sprangle from Austin, TX, age ~54 Get Report