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Ennis Takashi Ogawa

from Irvine, CA
Age ~60
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Also known as:
Ennis T Ogawa, Ennis Soo Ogawa, Ennis T Takashi, Ennis Choi, Takashi Ogawa Ennis, Takas Ogawa Ennis
Phone and address:
5002 Persimmon Ln, Irvine, CA 92612
Related to:
Young Mi Choi, 55Youngeun Choi, 50Sukkyoon ChoiYoungkee Cho, 54Soon Choi, 52
Connected to:
Akihisa Ogawa, 51Andrew S Ogawa, 81Aria E Ogawa, 34Bryan K Ogawa, 51Danielle Ogawa, 39Hideyo Ogawa, 81Hiroyuki Ogawa, 51I-Ling C Ogawa, 54Joseph Y Ogawa, 77Juri Ogawa, 42

Ennis Ogawa Phones & Addresses

  • 5002 Persimmon Ln, Irvine, CA 92612
  • 1701 Emilie Ln, Austin, TX 78731
  • 1701A Emilie Ln, Austin, TX 78731
  • 1705 Emilie Ln, Austin, TX 78731
  • 1210 Lorrain St, Austin, TX 78703 (512) 479-6527
  • 1200 Enfield Rd, Austin, TX 78703
  • Santa Ana, CA
  • Palo Alto, CA
  • Westminster, CA
  • 1701 Emilie Ln APT A, Austin, TX 78731

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Public records

Vehicle Records

Ennis Ogawa

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Address:
1701A Emilie Ln, Austin, TX 78731
VIN:
JTDKB20U597881431
Make:
TOYOTA
Model:
PRIUS
Year:
2009

Resumes

Resumes

Ennis Ogawa Photo 1

Associate Technical Director

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Location:
5002 Persimmon Ln, Irvine, CA 92612
Industry:
Semiconductors
Work:
A Start-Up
Associate Technical Director
Broadcom
Senior Principal Reliability Scientist
Texas Instruments May 2001 - Aug 2007
Reliability Engineer, Group Member of Technical Staff
University of Texas Austin Interconnect and Packaging Laboratory Jan 1994 - May 2001
Research Scientist
Education:
The University of Texas at Austin 1987 - 1994
Doctorates, Doctor of Philosophy, Physics, Philosophy Stanford University 1982 - 1986
Bachelors, Bachelor of Science, Physics
Skills:
Cmos
Reliability
Semiconductors
Microelectronics
Silicon
Analog
Failure Analysis
Characterization
Semiconductor Industry
Simulations
Ic
Yield
Thin Films
Process Integration
Product Engineering
Design of Experiments
Mixed Signal
Device Characterization
Integrated Circuits
Mems
Jmp
Languages:
English
Ennis Ogawa Photo 2

Reliability Engineer At Texas Instruments, Inc

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Location:
Austin, TX
Industry:
Semiconductors
Work:
Texas Instruments
Reliability Engineer at Texas Instruments, Inc

Publications

Us Patents

Multiple Copper Vias For Integrated Circuit Metallization And Methods Of Fabricating Same

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US Patent:
6919639, Jul 19, 2005
Filed:
Oct 15, 2002
Appl. No.:
10/271284
Inventors:
Paul S. Ho - Austin TX, US
Ennis Ogawa - Austin TX, US
Hideki Matsuhashi - Austin TX, US
Assignee:
The Board of Regents, the University of Texas System - Austin TX
International Classification:
H01L023/48
H01L023/52
H01L029/40
US Classification:
257774, 257758
Abstract:
Electromigration can be reduced in a copper-based metallization of an integrated circuit that includes a first copper-containing via that electrically connects an underlying conductive line and an overlying copper-containing line through an intervening insulating layer. Electromigration can be reduced by forming at least a second copper-containing via that electrically connects the underlying conductive line and the overlying copper-containing line through the intervening insulating layer, in parallel with the first copper-containing via. Multi-vias can provide redundancy to reduce early failure statistics. Moreover, since current is distributed among the vias, the electromigration driving force can be reduced and local Joule heating, in voids at the via interface, also may be reduced. Accordingly, even if via voids are formed, the structure may not fail by catastrophic thermal runaway due to Joule heating.

Versatile System For Diffusion Limiting Void Formation

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US Patent:
7033924, Apr 25, 2006
Filed:
Sep 16, 2003
Appl. No.:
10/662302
Inventors:
Ennis T. Ogawa - Austin TX, US
Joe W. McPherson - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/4763
US Classification:
438622
Abstract:
Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure () within a semiconductor device (). The device typically comprises a first interconnect (), and a second interconnect (). The primary structure is disposed between the first and second interconnects to electrically intercouple them. An active diffusion volume () is determined, within which the primary structure is located. A buffer structure () is disposed upon the first interconnect in proximity to the primary structure and adapted to buffer the primary via structure from diffusive voiding occurring at a contact point between the primary structure and the first interconnect.

Multiple Copper Vias For Integrated Circuit Metallization

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US Patent:
7078817, Jul 18, 2006
Filed:
Dec 13, 2004
Appl. No.:
11/010596
Inventors:
Paul S. Ho - Austin TX, US
Ennis Ogawa - Austin TX, US
Hideki Matsuhashi - Austin TX, US
Assignee:
Board of Regents, The University of Texas System - Austin TX
International Classification:
H01L 23/48
H01L 23/52
H01L 29/40
US Classification:
257774, 257758
Abstract:
Electromigration can be reduced in a copper-based metallization of an integrated circuit that includes a first copper-containing via that electrically connects an underlying conductive line and an overlying copper-containing line through an intervening insulating layer. Electromigration can be reduced by forming at least a second copper-containing via that electrically connects the underlying conductive line and the overlying copper-containing line through the intervening insulating layer, in parallel with the first copper-containing via. Multi-vias can provide redundancy to reduce early failure statistics. Moreover, since current is distributed among the vias, the electromigration driving force can be reduced and local Joule heating, in voids at the via interface, also may be reduced. Accordingly, even if via voids are formed, the structure may not fail by catastrophic thermal runaway due to Joule heating.

Electrically Inactive Via For Electromigration Reliability Improvement

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US Patent:
7566652, Jul 28, 2009
Filed:
Jul 24, 2006
Appl. No.:
11/491846
Inventors:
Young-Joon Park - Plano TX, US
Ennis Takashi Ogawa - Austin TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/20
US Classification:
438626, 438633, 438636, 438675, 438732, 438748, 257E21525, 257E21576, 257E21577, 257E21582, 257E23105, 257E23145, 257E23151, 257E23167, 257E23194
Abstract:
A semiconductor device includes a metal line formed in a first dielectric layer. A capping layer is formed the metal line. A second dielectric layer is formed over the first dielectric layer and the metal line. A first via is formed in the second dielectric layer and in contact with the metal line. A second via is formed in the second dielectric layer and in contact with the metal line , and is positioned a distance away from the first via. An electrically isolated via is formed in the second dielectric layer and in contact with the metal line and in between the first via and the second via. A third dielectric layer is formed over the second dielectric layer. First and second trenches are formed in the third dielectric layer and in contact with the first via and the second via , respectively. An isolated trench is formed in the third dielectric layer and in contact with the isolated via. The isolated via mitigates void formation and/or void migration during operation/conduction with electrons traveling from the first trench to the second trench via the metal line.

Capacitor-Based Method For Determining And Characterizing Scribe Seal Integrity And Integrity Loss

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US Patent:
7888776, Feb 15, 2011
Filed:
Jun 30, 2008
Appl. No.:
12/165419
Inventors:
Ennis T. Ogawa - Austin TX, US
Honglin Guo - Plano TX, US
Joe W. McPherson - Plano TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 23/544
US Classification:
257620, 257 48, 257E21523, 438460
Abstract:
One embodiment of the present invention relates to a scribe seal integrity detector. In this embodiment a scribe seal integrity detector is formed in an integrated circuit chip die. The scribe seal integrity comprises a scribe seal structure that extends along at least a portion of the periphery of the integrated chip die and a detector test structure. The detector test structure and the scribe seal form an electrical system configured to be accessed for a monitoring of one or more electrical parameters to determine and characterize scribe seal integrity of the integrated circuit chip die. The results of the electric measurements are analyzed for statistically relevant reliability characterization. Other methods and circuits are also disclosed.

Versatile System For Diffusion Limiting Void Formation

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US Patent:
20030122260, Jul 3, 2003
Filed:
Apr 1, 2002
Appl. No.:
10/113504
Inventors:
Ennis Ogawa - Austin TX, US
Joe McPherson - Plano TX, US
International Classification:
H01L021/4763
H01L023/48
H01L023/52
H01L029/40
US Classification:
257/774000, 438/618000, 438/622000, 257/758000, 257/700000
Abstract:
Disclosed is apparatus and method for decreasing diffusive damage effects to a primary structure () within a semiconductor device (). The device typically comprises a first interconnect (), and a second interconnect (). The primary structure is disposed between the first and second interconnects to electrically intercouple them. An active diffusion volume () is determined, within which the primary structure is located. A buffer structure () is disposed upon the first interconnect in proximity to the primary structure and adapted to buffer the primary via structure from diffusive voiding occurring at a contact point between the primary structure and the first interconnect.

Scalable Method For Identifying Cracks And Fractures Under Wired Or Ball Bonded Bond Pads

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US Patent:
20080246491, Oct 9, 2008
Filed:
Apr 6, 2007
Appl. No.:
11/784220
Inventors:
Ennis T. Ogawa - Austin TX, US
Daryl R. Heussner - Allen TX, US
Charles A. Odegard - McKinney TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
G01R 31/28
US Classification:
324519, 324526
Abstract:
In a method and system for testing a presence of a crack () in a device under test (DUT) (), a test system includes a bridge circuit (BC) () coupled to an electrical signal source (ESS) () capable of generating an electrical signal (). The BC () includes four impedances that are coupled in a bridge structure having two floating nodes (). The DUT () includes a test bond pad (TBP) () and an access bond pad (ABP) (). An impedance measurable across the TBP () and the ABP () is selectable as one of the four impedances. A stimulus () is provided to the DUT () to induce stress. A sensor () coupled across the two floating nodes () detects a change in a value of the electrical signal measured across the two floating nodes () in response to the stimulus (). The change is triggered by the presence of the crack () under the TBP () caused by the stress, the crack () changing the impedance.
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Ennis Takashi Ogawa from Irvine, CA, age ~60 Get Report