Elliot N Tan

8314034, Nov 20, 2012

Dec 23, 2010

12/978160

Elliot N. Tan - Portland OR, US
Michael K. Harper - Hillsboro OR, US

Intel Corporation - Santa Clara CA

H01L 21/302

438717, 438734, 438736, 438738, 257E21017, 257E2102

Methods for semiconductor device fabrication are provided. Features are created using spacers. Methods include creating a pattern comprised of at least two first features on the substrate surface, depositing a first conformal layer on the at least two first features, depositing a second conformal layer on the first conformal layer, partially removing the second conformal layer to partially expose the first conformal layer, and partially removing the first conformal layer from between the first features and the second conformal layer thereby creating at least two second features. Optionally the first conformal film is partially etched back before the second conformal film is deposited.

20060000796, Jan 5, 2006

Jun 30, 2004

10/882982

Elliot Tan - Portland OR, US
James Jeong - Beaverton OR, US
Qiang Fu - Portland OR, US

B44C 1/22
H01L 21/302

216037000, 216067000, 438706000, 438710000

In one embodiment a method is provided. The method, comprises performing at least one deposition operation to laminate portions of a patterned photoresist that experiences degradation when bombarded with an etchant plasma during a subsequent plasma etching operation and performing the plasma etching operation.

20090124084, May 14, 2009

Nov 14, 2007

11/940121

Elliot Tan - Portland OR, US
James Jeong - Portland OR, US

H01L 21/467

438699, 257E21486

A method for fabricating sub-resolution features on an integrated circuit comprises depositing a hard mask layer on a dielectric layer of a semiconductor substrate, patterning the hard mask layer to form hard mask structures that define trenches, etching trenches in the dielectric layer through the hard mask structures, thereby forming a first set of dielectric structures on the substrate, depositing a conformal layer on the substrate and the first set of dielectric structures, etching the conformal layer to form spacers adjacent to the first set of dielectric structures, depositing a second dielectric layer within the trenches, thereby forming a second set of dielectric structures on the substrate, and etching the spacers to form sub-resolution trenches between the dielectric structures of the first and second set.

20090170316, Jul 2, 2009

Dec 31, 2007

12/006204

Elliot Tan - Portland OR, US
Michael K. Harper - Hillsboro OR, US
James Jeong - Portland OR, US

H01L 21/308

438689, 257E21231

In general, in one aspect, a method includes forming a hard mask on a semiconductor substrate. A first resist layer is patterned on the hard mask as a first plurality of lines separated by a first defined pitch. The hard mask is etched to a portion of formed thickness to create a first plurality of fins in alignment with the first plurality of lines and the first resist layer is removed. A second resist layer is patterned on the hard mask as a second plurality of lines separated by a second defined pitch. The second plurality of lines is patterned between the first plurality of lines. The hard mask is etched to the portion of the formed thickness to create a second plurality of fins in alignment with the second plurality of lines. The first plurality of hard mask fins and the second plurality of hard mask fins are interwoven and have same thickness.

20090263751, Oct 22, 2009

Apr 22, 2008

12/148826

Swaminathan Sivakumar - Beaverton OR, US
Anna Lio - Portland OR, US
Elliot Tan - Portland OR, US
Charles Wallace - Portland OR, US
Anant Jahagirdar - Hillsboro OR, US

G03F 7/38

430323, 430324

Embodiments of methods for double patterning photoresist are generally described herein. Other embodiments may be described and claimed.

20220415897, Dec 29, 2022

Jun 25, 2021

17/358954

- Santa Clara CA, US
Travis W. LaJoie - Forest Grove OR, US
Elliot N. Tan - Portland OR, US
Kimberly Pierce - Beaverton OR, US
Shem Ogadhoh - West Linn OR, US
Abhishek A. Sharma - Portland OR, US
Bernhard Sell - Portland OR, US
Pei-Hua Wang - Hillsboro OR, US
Chieh-Jen Ku - Hillsboro OR, US

Intel Corporation - Santa Clara CA

H01L 27/108
H01L 29/786
H01L 29/66

A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization level. A first transistor and a laterally separated second transistor are on a same plane above the second interconnect line, where a gate of the first transistor is coupled to the first interconnect line and a gate of the second transistor is coupled to the second interconnect line. A first capacitor is coupled to a first terminal of the first transistor and a second capacitor is coupled to a first terminal of the second transistor. A third interconnect line couples a second terminal of the first transistor with a second terminal of the second transistor.

20220262722, Aug 18, 2022

May 2, 2022

17/735006

- Santa Clara CA, US
Robert L. BRISTOL - Portland OR, US
Kevin L. LIN - Beaverton OR, US
Florian GSTREIN - Portland OR, US
James M. BLACKWELL - Portland OR, US
Marie KRYSAK - Portland OR, US
Manish CHANDHOK - Beaverton OR, US
Paul A. NYHUS - Portland OR, US
Charles H. WALLACE - Portland OR, US
Curtis W. WARD - Hillsboro OR, US
Swaminathan SIVAKUMAR - Beaverton OR, US
Elliot N. TAN - Portland OR, US

H01L 23/528
H01L 23/522
H01L 23/532
H01L 27/088
H01L 29/78

Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

20220199628, Jun 23, 2022

Dec 21, 2020

17/129869

- Santa Clara CA, US
Sarah ATANASOV - Beaverton OR, US
Abhishek A. SHARMA - Hillsboro OR, US
Bernhard SELL - Portland OR, US
Chieh-Jen KU - Hillsboro OR, US
Arnab SEN GUPTA - Hillsboro OR, US
Matthew V. METZ - Portland OR, US
Elliot N. TAN - Portland OR, US
Hui Jae YOO - Portland OR, US
Travis W. LAJOIE - Forest Grove OR, US
Van H. LE - Portland OR, US
Pei-Hua WANG - Beaverton OR, US

H01L 27/108
H01L 29/786

An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.