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Ehren Michael Mannebach

from Beaverton, OR
Age ~35
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Also known as:
Ehren M Mannebach, Ehren Mannabach
Related to:
Michael P Kirchner, 45Marjorie A Mannebach, 88Patrick C Mannebach, 53Wayne C Mannebach, 89Beth E Mannebach, 64Maryjoce A MannebachMichael D Mannebach, 64Matthew P Mannebach, 34
Connected to:
Brian M Mannebach, 38Aaron J Manneh, 77Scott J Mannel, 44Steven Mannel, 64Burton D Mannell, 77Chelsea E Mannella, 38Heather L Mannello, 52Howard Mannella, 68James P Mannelly, 96Martha M Mannellino, 67

Ehren Mannebach Phones & Addresses

  • Beaverton, OR
  • Big Sky, MT
  • Portland, OR
  • Palo Alto, CA
  • Fond du Lac, WI
  • Madison, WI
  • 794 Country Club Ln, Fond du Lac, WI 54935 (920) 921-5661

Resumes

Resumes

Ehren Mannebach Photo 1

Components Research Integration Engineer

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Location:
4238 Rickeys Way, Palo Alto, CA 94306
Industry:
Semiconductors
Work:
Stanford University Mar 2017 - Aug 2017
Postdoctoral Researcher
Intel Corporation Mar 2017 - Aug 2017
Components Research Integration Engineer
Stanford University Sep 2012 - Mar 2017
Phd Candidate and Graduate Research Assistant
University of Wisconsin-Madison Oct 2008 - Jun 2012
Undergraduate Research Assistant
Oak Ridge National Laboratory Jun 2010 - Aug 2010
Summer Undergraduate Laboratory Internship
Education:
Stanford University 2012 - 2017
Doctorates, Doctor of Philosophy, Engineering, Materials Science, Philosophy University of Wisconsin - Madison 2007 - 2011
Bachelors, Bachelor of Science, Materials Science, Engineering
Skills:
Matlab
Materials Science
Scanning Electron Microscopy
Research
Nanotechnology
Nanomaterials
Afm
X Ray Diffraction
Data Analysis
Microsoft Office
Characterization
Optics
Tem
Microsoft Excel
Microsoft Word
Physics
Ued
Nonlinear Optics
Atomic Force Microscopy
Powerpoint
Optical Microscopy
Science
Laboratory Skills
Originlab
Ehren Mannebach Photo 2

Components Research Engineer

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Location:
Aurora, CO
Work:
Intel Corporation
Components Research Engineer
Education:
Stanford University 2012 - 2017
Doctorates, Doctor of Philosophy, Philosophy
Ehren Mannebach Photo 3

Ehren Mannebach

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Publications

Us Patents

Analogue Ionic Liquids For The Separation And Recovery Of Hydrocarbons From Particulate Matter

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US Patent:
20120048783, Mar 1, 2012
Filed:
Oct 4, 2011
Appl. No.:
13/252523
Inventors:
Paul Painter - Boalsburg PA, US
Phil Williams - State College PA, US
Ehren Mannebach - Fond du Lac WI, US
Aron Lupinsky - State College PA, US
Assignee:
PENN STATE RESEARCH FOUNDATION - UNIVERSITY PARK PA
International Classification:
C10G 1/04
US Classification:
208390
Abstract:
Systems, methods and compositions for the separation and recovery of hydrocarbons from particulate matter are herein disclosed. According to one embodiment, a method includes contacting particulate matter with at least one analogue ionic liquid. The particulate matter contains at least one hydrocarbon and at least one solid particulate. When the particulate matter is contacted with the analogue ionic liquid, the hydrocarbon dissociates from the solid particulate to form a multiphase system.

Analogue Ionic Liquids For The Separation And Recovery Of Hydrocarbons From Particulate Matter

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US Patent:
20140054200, Feb 27, 2014
Filed:
Nov 1, 2013
Appl. No.:
14/070078
Inventors:
Phil WILLIAMS - State College PA, US
Ehren MANNEBACH - Fond du Lac WI, US
Aron LUPINSKY - State College PA, US
Assignee:
The Penn State Research Foundation - University Park PA
International Classification:
C10G 1/04
US Classification:
208390
Abstract:
Systems, methods and compositions for the separation and recovery of hydrocarbons from particulate matter are herein disclosed. According to one embodiment, a method includes contacting particulate matter with at least one analogue ionic liquid. The particulate matter contains at least one hydrocarbon and at least one solid particulate. When the particulate matter is contacted with the analogue ionic liquid, the hydrocarbon dissociates from the solid particulate to form a multiphase system.

Systems, Methods And Compositions For The Separation And Recovery Of Hydrocarbons From Particulate Matter

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US Patent:
8603326, Dec 10, 2013
Filed:
Aug 11, 2010
Appl. No.:
12/854553
Inventors:
Paul Painter - Boalsburg PA, US
Phil Williams - State College PA, US
Ehren Mannebach - Fond du Lac WI, US
Aron Lupinsky - State College PA, US
Assignee:
The Penn State Research Foundation - University Park PA
International Classification:
C10G 1/04
US Classification:
208390, 208391, 208424, 208425, 208428
Abstract:
Systems, methods and compositions for the separation and recovery of hydrocarbons from particulate matter are herein disclosed. According to one embodiment, a method includes contacting particulate matter with at least one ionic liquid. The particulate matter contains at least one hydrocarbon and at least one solid particulate. When the particulate matter is contacted with the ionic liquid, the hydrocarbon dissociates from the solid particulate to form a multiphase system.

Backside Contacts For Semiconductor Devices

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US Patent:
20220352032, Nov 3, 2022
Filed:
Jul 15, 2022
Appl. No.:
17/866122
Inventors:
- Santa Clara CA, US
Ehren MANNEBACH - Beaverton OR, US
Anh PHAN - Beaverton OR, US
Richard E. SCHENKER - Portland OR, US
Stephanie A. BOJARSKI - Beaverton OR, US
Willy RACHMADY - Beaverton OR, US
Patrick R. MORROW - Portland OR, US
Jeffrey D. BIELEFELD - Forest Grove OR, US
Gilbert DEWEY - Beaverton OR, US
Hui Jae YOO - Portland OR, US
Assignee:
INTEL CORPORATION - Santa Clara CA
International Classification:
H01L 21/8234
H01L 27/088
H01L 29/78
H01L 29/06
H01L 23/532
H01L 23/48
Abstract:
Backside contact structures include etch selective materials to facilitate backside contact formation. An integrated circuit structure includes a frontside contact region, a device region below the frontside contact region, and a backside contact region below the device region. The device region includes a transistor. The backside contact region includes a first dielectric material under a source or drain region of the transistor, a second dielectric material laterally adjacent to the first dielectric material and under a gate structure of the transistor. A non-conductive spacer is between the first and second dielectric materials. The first and second dielectric materials are selectively etchable with respect to one another and the spacer. The backside contact region may include an interconnect feature that, for instance, passes through the first dielectric material and contacts a bottom side of the source/drain region, and/or passes through the second dielectric material and contacts the gate structure.

Gate-All-Around Integrated Circuit Structures Having Depopulated Channel Structures Using Selective Bottom-Up Approach

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US Patent:
20220262796, Aug 18, 2022
Filed:
Apr 27, 2022
Appl. No.:
17/731110
Inventors:
- Santa Clara CA, US
Ehren MANNEBACH - Beaverton OR, US
Cheng-Ying HUANG - Portland OR, US
Marko RADOSAVLJEVIC - Portland OR, US
International Classification:
H01L 27/092
H01L 29/06
H01L 29/417
H01L 29/423
H01L 29/786
H01L 29/66
H01L 21/02
H01L 21/8238
Abstract:
Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.

Leave-Behind Protective Layer Having Secondary Purpose

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US Patent:
20220246608, Aug 4, 2022
Filed:
Apr 21, 2022
Appl. No.:
17/726412
Inventors:
- Santa Clara CA, US
Anh PHAN - Beaverton OR, US
Ehren MANNEBACH - Tigard OR, US
Cheng-Ying HUANG - kPortland OR, US
Stephanie A. BOJARSKI - Beaverton OR, US
Gilbert DEWEY - Beaverton OR, US
Orb ACTON - Portland OR, US
Willy RACHMADY - Beaverton OR, US
International Classification:
H01L 27/088
H01L 29/423
H01L 29/08
H01L 21/762
H01L 23/528
H01L 29/78
H01L 29/06
Abstract:
Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.

Cmos Architecture With Thermally Stable Silicide Gate Workfunction Metal

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US Patent:
20230090092, Mar 23, 2023
Filed:
Sep 22, 2021
Appl. No.:
17/448382
Inventors:
Aaron D. Lilak - Beaverton OR, US
Orb Acton - Portland OR, US
Cheng-Ying Huang - Hillsboro OR, US
Gilbert Dewey - Beaverton OR, US
Ehren Mannebach - Tigard OR, US
Anh Phan - Beaverton OR, US
Willy Rachmady - Beaverton OR, US
Jack T. Kavalieros - Portland OR, US
International Classification:
H01L 27/12
H01L 21/84
Abstract:
An integrated circuit having a transistor architecture includes a first semiconductor body and a second semiconductor body. The first and second semiconductor bodies are arranged vertically (e.g., stacked configuration) or horizontally (e.g., forksheet configuration) with respect to each other, and separated from one another by insulator material, and each can be configured for planar or non-planar transistor topology. A first gate structure is on the first semiconductor body, and includes a first gate electrode and a first high-k gate dielectric. A second gate structure is on the second semiconductor body, and includes a second gate electrode and a second high-k gate dielectric. In an example, the first gate electrode includes a layer comprising a compound of silicon and one or more metals; the second gate structure may include a silicide workfunction layer, or not. In one example, the first gate electrode is n-type, and the second gate electrode is p-type.

Gate-All-Around Integrated Circuit Structures Having Depopulated Channel Structures Using Selective Bottom-Up Approach

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US Patent:
20210407997, Dec 30, 2021
Filed:
Jun 25, 2020
Appl. No.:
16/912113
Inventors:
- Santa Clara CA, US
Ehren MANNEBACH - Beaverton OR, US
Cheng-Ying HUANG - Portland OR, US
Marko RADOSAVLJEVIC - Portland OR, US
International Classification:
H01L 27/092
H01L 29/06
H01L 29/417
H01L 29/423
H01L 29/786
H01L 21/02
H01L 21/8238
H01L 29/66
Abstract:
Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.
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Ehren Michael Mannebach from Beaverton, OR, age ~35 Get Report