Edward C Dasse

55043690, Apr 2, 1996

Nov 21, 1994

8/342960

Edward C. Dasse - Austin TX
Robert W. Bollish - Austin TX
Alfredo Figueroa - Austin TX
James H. Carlquist - Austin TX
Thomas R. Yarbrough - Buda TX
Charles F. Toewe - Austin TX
Kelvin L. Holub - Austin TX
Marcus R. Burton - Dripping Springs TX
Kenneth J. Long - Austin TX
Walid S. Ballouli - Austin TX

Motorola Inc. - Schaumburg IL

H01L 2166
G01R 3100
G01R 3128

257620

A semiconductor wafer (20) having integrated circuit dice (22), wafer conductors (42-47, 50-53), and wafer contact pads (38) formed thereon. The wafer conductors (42-47, 50-53) are used to transfer electrical signals to and from the integrated circuit dice (22) on semiconductor wafer (20) so that wafer level testing and burn-in can be performed on the integrated circuit dice (22). In accordance with one embodiment of the present, each wafer conductor (45, 52) is electrically coupled to the same bonding pad (78) on each integrated circuit dice (22). Each wafer conductor (42-47, 50-53) includes at least a portion of conductor (42-47) which overlies the upper surface of at least one integrated circuit dice (22).

55942733, Jan 14, 1997

Jun 7, 1995

8/482330

Edward C. Dasse - Austin TX
Donald R. Kost - Round Rock TX
Lawrence J. Day - Manchaca TX

Motorola Inc. - Schaumburg IL

G01R 3100
G01R 3128
H01L 2166

257620

Wafer level testing of a wafer (500) is accomplished by dividing the integrated circuits of the wafer into a plurality of segmented bus regions (514, 516, and 518 for example). Each bus region is formed having its own set of test conductors (520-530) wherein each set of test conductors are isolated from all other sets of test conductors on the wafer. Each test conductor has at least one contact pad (531-546) where each contact pad lies within a periphery of the integrated circuits' active areas. By forming pads over ICs and by sub-dividing the bus structure of test conductive lines, more high powered ICs can be tested in a wafer-level manner with fewer problems associated with speed, power, throughput, and routing problems. In addition, all contact pads are formed within the periphery of the ICs but no contact pads are formed over active circuitry so that yield is improved.

53995058, Mar 21, 1995

Jul 23, 1993

8/096094

Edward C. Dasse - Austin TX
Robert W. Bollish - Austin TX
Alfredo Figueroa - Austin TX
James H. Carlquist - Austin TX
Thomas R. Yarbrough - Buda TX
Charles F. Toewe - Austin TX
Kelvin L. Holub - Austin TX
Marcus R. Burton - Dripping Springs TX
Kenneth J. Long - Austin TX
Walid S. Ballouli - Austin TX
Shih K. Cheng - Scottsdale AZ

Motorola, Inc. - Schaumburg IL

H01L 2166

437 8

A semiconductor wafer (20) having integrated circuit dice (22), wafer conductors (42-47, 50-53), and wafer contact pads (38) formed thereon. The wafer conductors (42-47, 50-53) are used to transfer electrical signals to and from the integrated circuit dice (22) on semiconductor wafer (20) so that wafer level testing and burn-in can be performed on the integrated circuit dice (22). In accordance with one embodiment of the present, each wafer conductor (45, 52) is electrically coupled to the same bonding pad (78) on each integrated circuit dice (22). Each wafer conductor (42-47, 50-53) includes at least a portion of conductor (42-47) which overlies the upper surface of at least one integrated circuit dice (22).

56545886, Aug 5, 1997

Jun 7, 1995

8/487671

Edward C. Dasse - Austin TX
Robert W. Bollish - Austin TX
Alfredo Figueroa - Austin TX
James H. Carlquist - Austin TX
Thomas R. Yarbrough - Buda TX
Charles F. Toewe - Austin TX
Kelvin L. Holub - Austin TX
Marcus R. Burton - Dripping Springs TX
Kenneth J. Long - Austin TX
Walid S. Ballouli - Austin TX
Shih King Cheng - Scottsdale AZ

Motorola Inc. - Schaumburg IL

G01R 3100
G01R 3128
H01L 2166

257754

Wafer level testing of a wafer (500) is accomplished by dividing the integrated circuits of the wafer into a plurality of segmented bus regions (514, 516, and 518 for example). Each bus region is formed having its own set of test conductors (520-530) wherein each set of test conductors are isolated from all other sets of test conductors on the wafer. Each test conductor has at least one contact pad (531-546) where each contact pad lies within a periphery of the integrated circuits' active areas. By forming pads over ICs and by sub-dividing the bus structure of test conductive lines, more high powered ICs can be tested in a wafer-level manner with fewer problems associated with speed, power, throughput, and routing problems.