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Edward T Bee

from Palo Alto, CA
Age ~48
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Also known as:
Edward Han Bee, Ed T Bee, Edward Hanbee, Bee Edward
Phone and address:
930 Bautista Ct, Palo Alto, CA 94303
(650) 814-5188
Related to:
Helena M Bee, 50Barry C Bee, 87Derek Chan, 41Edwrd T BeeDenise BeeDerek Chan, 46Lily BeeEllen Y Bee, 85Denise K Chan, 46Billy J Bee, 57Albert L Chan, 75Lily L Bee, 76Grace Chan, 74
Connected to:
Allen M Bee, 34Arlinda Bee, 51Barbara J Bee, 45Beatriz C Bee, 68Bradley Bee, 36Catherine A Bee, 51Clifford D Bee, 42Cory A Bee, 30Danny J Bee, 60Doris M Bee, 90

Edward Bee Phones & Addresses

  • 930 Bautista Ct, Palo Alto, CA 94303 (650) 814-5188
  • 6255 Arby Ave, Las Vegas, NV 89118 (702) 247-9661
  • 6255 W Arby Ave UNIT 205, Las Vegas, NV 89118
  • 194 Exeter Ave, San Carlos, CA 94070
  • 1873 Saddlewood Dr, Concord, CA 94521
  • San Francisco, CA
  • Houston, TX
  • Carmel Valley, CA
  • Los Altos, CA
  • San Mateo, CA
  • San Luis Obispo, CA

Work

Company: Eze castle software Sep 2005 Address: San Francisco & Chicago Position: Director western and midwestern u.s.

Education

Degree: B.S. Magna Cum Laude School / High School: California Polytechnic State University-San Luis Obispo 1994 to 2000 Specialities: Economics & International Business

Awards

Magna Cum Laude • Beta Gamma Sigma National Honor Society • Golden Key National Honor Society

Industries

Financial Services

Resumes

Resumes

Edward Bee Photo 1

Director At Eze Software Group

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Position:
Director Western and Midwestern U.S. at Eze Castle Software
Location:
San Francisco Bay Area
Industry:
Financial Services
Work:
Eze Castle Software - San Francisco & Chicago since Sep 2005
Director Western and Midwestern U.S.
Universal Computer Systems - San Francisco Bay Area Oct 2001 - Sep 2005
Regional Systems Consultant
Yahoo! Jun 2000 - Oct 2001
Analyst
Education:
California Polytechnic State University-San Luis Obispo 1994 - 2000
B.S. Magna Cum Laude, Economics & International Business
Honor & Awards:
Magna Cum Laude Beta Gamma Sigma National Honor Society Golden Key National Honor Society

Business Records

Name / Title
Company / Classification
Phones & Addresses
Edward Bee
M
Backhaul Management Group, LLC
2360 Corporate Cir, Henderson, NV 89074
Edward Bee
President
B + B IMEX, INCORPORATED
1873 Saddlewood Dr, Concord, CA 94521

Publications

Us Patents

Synchronizing Signal Active Filter And Method

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US Patent:
55283039, Jun 18, 1996
Filed:
Nov 1, 1993
Appl. No.:
8/146598
Inventors:
Edward C. Bee - San Jose CA
Stephen F. Colaco - Santa Cruz CA
Assignee:
Elantec, Inc. - Milpitas CA
International Classification:
H04N 508
US Classification:
348531
Abstract:
An integrated active filter and sync separator circuit operates on precision internal reference sources to set the filter cut off frequency as a function of resistance of an external resistor. The active filter eliminates the source of sync tip crushing attributable to conventional clamping circuits associated with sync pulse detectors, and also provides sync pulses substantially devoid of time-variant jitter.

Class Ab Complementary Output Stage

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US Patent:
54753430, Dec 12, 1995
Filed:
Aug 15, 1994
Appl. No.:
8/290362
Inventors:
Edward C. Bee - San Jose CA
Assignee:
Elantec, Inc. - Milpitas CA
International Classification:
H03F 326
US Classification:
330255
Abstract:
A class AB complementary output stage provides maximum output voltage swings and high load currents with minimum power dissipation. The output stage includes a first bias circuit that generates a pair of voltage nodes with a resistor controlled bias current. A second bias circuit comprises four current sources the outputs of which are coupled pair-wise across a resistor to form a pair of high impedance nodes at the resistor terminals. The voltage nodes of the first bias circuit establish bias currents in a differential input stage and in a pair of current sources of the second bias circuit. The outputs of the differential input stage drive the inputs of second pair of current sources in the second bias circuit, which provide drive current to the high impedance nodes. The output circuit comprises a pair of complementary common source transistors, the gates (bases) of which are driven by the high impedance nodes of the second bias circuit.

Current Product Limit Detector

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US Patent:
43497551, Sep 14, 1982
Filed:
Feb 11, 1980
Appl. No.:
6/120509
Inventors:
Edward C. Bee - Sunnyvale CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
G06G 712
G06G 716
US Classification:
307492
Abstract:
A circuit for detecting when the product of two independent currents equals or exceeds a predetermined upper limit is disclosed. The circuit includes a load current source for providing a load current for defining the predetermined upper limit; a differential amplifier including first and second transistors having their emitters connected in common to an emitter current source, wherein the collector of the first transistor is connected to the load current source for providing an output signal at the collector that changes state when the collector current is not less than the load current; a first combination of components for providing a voltage signal at the base of the first transistor that is representative of the natural logarithm of the reciprocal of a first independent current; and a second combination of components for providing a voltage signal at the base of the second transistor that is representative of the natural logarithm of a second independent current. Accordingly the collector current of the first transistor is proportional to the natural logarithm of the product of the first and second independent currents, and when the collector current equals or exceeds the value of the load current, the output signal is provided at the collector of the first transistor to indicate that the predetermined upper limit has been exceeded.

Differential Amplifier Multiplexer

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US Patent:
54263964, Jun 20, 1995
Filed:
Apr 7, 1994
Appl. No.:
8/225131
Inventors:
Edward C. Bee - San Jose CA
Assignee:
Elantec, Inc. - Milpitas CA
International Classification:
H03F 345
US Classification:
330253
Abstract:
A multiplexer circuit includes pairs of control elements such as CMOS transistors serially connected between common circuit nodes to conduct current therebetween in response to one of each pair of control elements being selectively biased to conductive or non-conductive states by an applied control signal. The current enabled to flow between circuit nodes through a pair of control elements biased to conductive state is determined by the magnitude of an applied signal, and a current-difference circuit compares the current flowing between circuit nodes with a reference current to produce an output signal representative of the applied signal which is selected in response to an applied control signal.
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Edward T Bee from Palo Alto, CA, age ~48 Get Report