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Eddy T Tjhia

from Davis, CA
Age ~79
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Also known as:
Eddy Te Tjhia, Eddy Viola Tjhia, Edward T Tjhia, Eddy Thjia, Thia Eddy
Related to:
Kei Ho Pak, 62Crystal K Tjhia, 41Cynthia K Tjhia, 39Rogerkin On Tjhia, 37Viola C Tjhia, 69Albert Tjhia
Connected to:
Susy Tjhin, 53Katherina Tjin, 36Max F Tjin, 74Herbert S Tjiptadjaja, 57Liang G Tjoa, 61Michelle J Tjoa, 28Ping A Tjoa, 80Rex F Tjoa, 47Triyono W Tjokronegoro, 43Kevin L Tjoland, 62

Eddy Tjhia Phones & Addresses

  • Davis, CA
  • Bloomington, IN
  • 738 Remington Ct, Sunnyvale, CA 94087 (408) 481-9649
  • Cupertino, CA
  • San Francisco, CA
  • Yolo, CA
  • 738 W Remington Dr, Sunnyvale, CA 94087

Education

Degree: Doctorates, Doctor of Philosophy School / High School: Techinal University Stuttgart 1972 to 1976 Specialities: Physics

Resumes

Resumes

Eddy Tjhia Photo 1

Eddy Tjhia

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Education:
Techinal University Stuttgart 1972 - 1976
Doctorates, Doctor of Philosophy, Physics

Publications

Us Patents

Vertical Structure For Semiconductor Wafer-Level Chip Scale Packages

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US Patent:
6392290, May 21, 2002
Filed:
Apr 7, 2000
Appl. No.:
09/545287
Inventors:
Y. Mohammed Kasem - Santa Clara CA
Yueh-Se Ho - Sunnyvale CA
Lee Shawn Luo - San Jose CA
Chang-Sheng Chen - Santa Clara CA
Eddy Tjhia - Sunnyvale CA
Bosco Lan - Fremont CA
Jacek Korec - San Jose CA
Anup Bhalla - Santa Clara CA
Assignee:
Siliconix Incorporated - Santa Clara CA
International Classification:
H01L 2302
US Classification:
257678, 257774
Abstract:
In a semiconductor package for a chip having terminals on both sides, for example, a power MOSFET in which the gate and source terminals are on the front side and the drain terminal is on the back side, electrical contact is made with the back side terminal by extending vias, which can take the form of trenches, holes or other cavities, either entirely or patrially through the chip. The vias are filled with a metal or other electrically conductive material. The process is performed on the chips in a wafer simultaneously. The resulting package is compact and economical to manufacture and can readily be mounted, flip-chip style, on a printed circuit board.

Semiconductor Chip Package

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US Patent:
D466873, Dec 10, 2002
Filed:
Oct 31, 2001
Appl. No.:
29/151024
Inventors:
Frank Kuo - Kaoshiung, TW
Eddy Tjhia - Sunnyvale CA
Assignee:
Siliconix Incorporated - Santa Clara CA
International Classification:
1303
US Classification:
D13182

Semiconductor Chip Package

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US Patent:
D472528, Apr 1, 2003
Filed:
Oct 31, 2001
Appl. No.:
29/151069
Inventors:
Frank Kuo - Kaoshiung, TW
Eddy Tjhia - Sunnyvale CA
Assignee:
Siliconix incorporated - Santa Clara CA
International Classification:
1303
US Classification:
D13182

High-Power Semiconductor Die Packages With Integrated Heat-Sink Capability And Methods Of Manufacturing The Same

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US Patent:
7800219, Sep 21, 2010
Filed:
Jan 2, 2008
Appl. No.:
11/968602
Inventors:
Oseob Jeon - Seoul, KR
Chung-Lin Wu - San Jose CA, US
Eddy Tjhia - Sunnyvale CA, US
Bigildis C. Dosdos - San Jose CA, US
Assignee:
Fairchild Semiconductor Corporation - South Portland ME
International Classification:
H01L 23/34
H01L 23/10
US Classification:
257706, 257E21499, 257669, 257701, 438106, 438107
Abstract:
An exemplary semiconductor die package of the invention has a metal-oxide substrate disposed between a first surface of a semiconductor die and a heat-sinking component, with a conductive die clip or one or more electrical interconnect traces disposed between the metal-oxide substrate and the first surface of the semiconductor die. The heat-sinking component may comprise a heat sink, or an adaptor plate to which a heat sink may be coupled. The conductive die clip or electrical trace(s) provides electrical connection(s) to the first surface of the semiconductor die, while the metal-oxide substrate electrically insulates the die from the heat-sinking component, and provides a path of high thermal conductivity between the die and the heat-sinking component. The second surface of the semiconductor die may be left free to connect to a circuit board, or a leadframe or interconnect substrate may be attached to it.

Semiconductor Dice With Backside Trenches Filled With Elastic Material For Improved Attachment, Packages Using The Same, And Methods Of Making The Same

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US Patent:
7960800, Jun 14, 2011
Filed:
Dec 12, 2008
Appl. No.:
12/334331
Inventors:
Michael D. Gruenhagen - Salt Lake City UT, US
Suku Kim - South Jordan UT, US
James J. Murphy - South Jordan UT, US
Eddy Tjhia - Sunnyvale CA, US
Chung-Lin Wu - San Jose CA, US
Mark Larsen - Sandy UT, US
Douglas E. Dolan - York ME, US
Assignee:
Fairchild Semiconductor Corporation - South Portland ME
International Classification:
H01L 27/088
US Classification:
257401, 257E21585, 257417, 257673, 257678, 438106, 438284, 438286
Abstract:
Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.

Semiconductor Die Structures For Wafer-Level Chipscale Packaging Of Power Devices, Packages And Systems For Using The Same, And Methods Of Making The Same

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US Patent:
8058732, Nov 15, 2011
Filed:
Nov 20, 2008
Appl. No.:
12/275086
Inventors:
Michael D. Gruenhagen - Salt Lake City UT, US
Suku Kim - South Jordan UT, US
James J. Murphy - South Jordan UT, US
Ihsiu Ho - Salt Lake City UT, US
Eddy Tjhia - Sunnyvale CA, US
Chung-Lin Wu - San Jose CA, US
Mark Larsen - Sandy UT, US
Rohit Dikshit - Herriman UT, US
Assignee:
Fairchild Semiconductor Corporation - South Portland ME
International Classification:
H01L 23/48
US Classification:
257774, 257773, 257698, 257E25017, 257E23145, 257E21549, 257E21577, 257E21585
Abstract:
Disclosed are semiconductor die structures that enable a die having a vertical power device to be packaged in a wafer-level chip scale package where the current-conducting terminals are present at one surface of the die, and where the device has very low on-state resistance. In an exemplary embodiment, a trench and an aperture are formed in a backside of a die, with the aperture contacting a conductive region at the top surface of the die. A conductive layer and/or a conductive body may be disposed on the trench and aperture to electrically couple the backside current-conducting electrode of the device to the conductive region. Also disclosed are packages and systems using a die with a die structure according to the invention, and methods of making dice with a die structure according to the invention.

High-Power Semiconductor Die Packages With Integrated Heat-Sink Capability And Methods Of Manufacturing The Same

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US Patent:
8193043, Jun 5, 2012
Filed:
Sep 15, 2010
Appl. No.:
12/883044
Inventors:
Oseob Jeon - Seoul, KR
Chung-Lin Wu - San Jose CA, US
Eddy Tjhia - Sunnyvale CA, US
Bigildis C. Dosdos - San Jose CA, US
Assignee:
Fairchild Semiconductor Corporation - South Portland ME
International Classification:
H01L 21/00
US Classification:
438125, 257E21499, 257705, 257706, 257718, 438107, 438122
Abstract:
An exemplary semiconductor die package of the invention has a metal-oxide substrate disposed between a first surface of a semiconductor die and a heat-sinking component, with a conductive die clip or one or more electrical interconnect traces disposed between the metal-oxide substrate and the first surface of the semiconductor die. The heat-sinking component may comprise a heat sink, or an adaptor plate to which a heat sink may be coupled. The conductive die clip or electrical trace(s) provides electrical connection(s) to the first surface of the semiconductor die, while the metal-oxide substrate electrically insulates the die from the heat-sinking component, and provides a path of high thermal conductivity between the die and the heat-sinking component. The second surface of the semiconductor die may be left free to connect to a circuit board, or a leadframe or interconnect substrate may be attached to it.

Semiconductor Dice With Backside Trenches Filled With Elastic Material For Improved Attachment, Packages Using The Same, And Methods Of Making The Same

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US Patent:
8598035, Dec 3, 2013
Filed:
Jun 2, 2011
Appl. No.:
13/151495
Inventors:
Michael D. Gruenhagen - Salt Lake City UT, US
Suku Kim - South Jordan UT, US
James J. Murphy - South Jordan UT, US
Eddy Tjhia - Sunnyvale CA, US
Chung-Lin Wu - San Jose CA, US
Mark Larsen - Sandy UT, US
Douglas E. Dolan - York ME, US
Assignee:
Fairchild Semiconductor Corporation - San Jose CA
International Classification:
H01L 21/44
US Classification:
438669, 438284, 438652, 257E21158, 257341, 257678
Abstract:
Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice.
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Eddy T Tjhia from Davis, CA, age ~79 Get Report